Renesas RL78 - Page 35

RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 35 of 85
Feb. 15, 2017
TAU0 All Interru
p
ts Disable
・Interrupt request flag register (MK0H/MK1L)
Disable all TAU0 interrupts.
・Interrupt request flag register (IF0H/IF1L)
Clear TAU interrupt request flags.
Symbol: MK0H
7 6 5 4 3 2 1 0
STMK1
CSIMK10
IICMK10
TMMK00 SREMK0 1 1
SRMK0
CSIMK01
IICMK01
STMK0
CSIMK00
IICMK00
PMK6
x 1 x x x x x x
Bit 6
TMMK00 Interrupt processing control
0 Interrupt processing enabled
1 Interrupt processing disabled
Symbol: MK1L
7 6 5 4 3 2 1 0
TMMK03 TMMK02 TMMK01 TMMK03H TMMK01H IICAMK0 SREMK1
SRMK1
CSIMK11
IICMK11
1 1 1 1 1 x x x
Bit 7 - 3 (n = 1 - 3)(m = 1, 3)
TMMK0n
TMMK0mH
Interrupt processing control
0 Enables interrupt processing
1 Disables interrupt processing
Symbol: IF0H
7 6 5 4 3 2 1 0
ST1IF
CSIIF10
IICIF10
TMIF00 SREIF0 0 0
SRIF0
CSIIF01
IICIF01
STIF0
CSIIF00
IICIF00
PIF6
x 0 x x x x x x
Bit 6
TMIF00 Interrupt request flag
0 Interrupt request signal not generated
1 Interrupt request signal generated, goes to interrupt request state
Symbol: IF1L
7 6 5 4 3 2 1 0
TMIF03 TMIF02 TMIF01 TMIF03H TMIF01H IICAIF0 SREIF1
SRIF1
CSIIF11
IICIF11
0 0 0 0 0 x x x
Bit 7 - 3 (n = 1 - 3)(m = 1, 3)
TMIF0n
TMIF0mH
Interrupt request flag
0 Interrupt request signal not generated
1 Interrupt request signal generated, goes to interrupt request state