RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 37 of 85
Feb. 15, 2017
Symbol: TMR01
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKS
011
CKS
010
0 CCS
01
SPLIT
01
STS
012
STS
011
STS
010
CIS
011
CIS
010
0 0 MD
013
MD
012
MD
011
MD
010
0 0 x 0 0 0 0 0 0 0 x x 0 0 0 0
Bit 15 – 14
CKS
011
CKS
010
Selection of operation clock (f
MCK
) for channel n
0 0 Operation clock CKm0 set in timer clock selection register m (TPSm)
0 1 Operation clock CKm2 set in timer clock selection register m (TPSm)
1 0 Operation clock CKm1 set in timer clock selection register m (TPSm)
1 1 Operation clock CKm3 set in timer clock selection register m (TPSm)
Bit 12
CCS01 Selection of channel n operation clock (f
TCLK
)
0 Operation clock (f
MCK
) set in bits CKSmn0 and CKSmn1
1 Valid edge of input signal from TImn pin
Bit 11
SPLIT01 Selection of 8-bit/16-bit timer operation for channels 1 and 3
0 Operates as 16-bit timer
1 Operates as 8-bit timer
Bit 10 – 8
STS
012
STS
011
STS
010
Setting start or capture trigger of channel n
0 0 0 Only software trigger start is valid (other trigger sources are unselected)
0 0 1 Valid edge of Tlmn pin input is used as both the start trigger and capture trigger
0 1 0 Both edges of Tlmn pin input are used as the start trigger and capture trigger
1 0 1
Interrupt signal of master channel is used (when using slave channel with simultaneous channel
operation function)
Other than above Setting prohibited
・Timer mode register 01 (TMR01)
Set TAU0 channel 1 as follows:
・Operation clock: CK00(24MHz)
・Operate as 16-bit timer
・Software trigger start
・TI01 pin valid edge: falling
・Interval timer mode
TAU0 Channel 1 Initialization
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