Renesas RL78 - Page 39

RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 39 of 85
Feb. 15, 2017
・Timer data register 01 (TDR01)
Set TAU0 channel 1 compare value to 1295H.
TAU0 Channel 1 Compare Value Setting
・Timer output level register 0 (TOL0)
Set positive logic output.
TAU0 Channel 1 Out
p
ut Level Control Settin
g
Symbol: TOL0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 TOL
03
TOL
02
TOL
01
0
x x x x x x x x x x x x x x 0 x
Bit 1
TOL
01
Control of channel n timer output level
0 Positive logic output (active-high)
1 Negative logic output (active-low)
・Timer output mode register 0 (TOM0)
Set the master channel mode output mode.
TAU0 Channel 1 Out
p
ut Mode Settin
g
Symbol: TDR01
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1
Symbol: TOM0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 TOM
03
TOM
02
TOM
01
0
x x x x x x x x x x x x x x 0 x
Bit 1
TOM
01
Control of channel n timer output mode
0 Master channel output mode
1 Slave channel output mode