RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 41 of 85
Feb. 15, 2017
・Timer mode register 03 (TMR03)
Set TAU0 channel 3 as follows:
・Operation clock: CK00(24MHz)
・Single channel operations
・TI03 pin valid edge used as start trigger and capture trigger
・TI03 pin valid edge: rising
・Input pulse width measurement mode
・Timer interrupt not generated when count star count starts
TAU0 Channel 3 Initialization
Symbol: TMR03
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKS
031
CKS
030
0 CCS
03
SPLIT
03
STS
032
STS
031
STS
030
CIS
031
CIS
030
0 0 MD
033
MD
032
MD
031
MD
030
0 0 x 0 0 0 0 1 0 1 x x 0 1 0 0
Bit 15 – 14
CKS
031
CKS
030
Selection of channel n operation clock (f
MCK
)
0 0 Operation clock CKm0 set in timer clock selection register m (TPSm)
0 1 Operation clock CKm2 set in timer clock selection register m (TPSm)
1 0 Operation clock CKm1 set in timer clock selection register m (TPSm)
1 1 Operation clock CKm3 set in timer clock selection register m (TPSm)
Bit 12
CCS03 Selection of channel n operation clock (f
TCLK
)
0 Operation clock (f
MCK
) set in bits CKSmn0 and CKSmn1
1 Valid edge of input signal from TImn pin
Bit 11
SPLIT03 Selection of 8 or 16-bit timer operation for channels 1 and 3
0 Operation as 16-bit timer
1 Operation as 8-bit timer
Bit 10 – 8
STS
032
STS
031
STS
030
Setting start trigger and capture trigger for channel n
0 0 0 Only software trigger start is valid (other trigger sources are unselected)
0 0 1
Valid edge of Tlmn pin input is used as both the start trigger and capture
trigger
0 1 0 Both edges of Tlmn pin input are used as the start trigger and capture trigger
1 0 1
Interrupt signal of master channel is used (when using slave channel with simultaneous channel
operation function)
Other than above Setting prohibited
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