Renesas RL78 - Page 42

RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 42 of 85
Feb. 15, 2017
Bit 7 – 6
CIS
031
CIS
030
Selection of Tlmn pin input valid edge
0 0 Falling edge
0 1 Rising edge
1 0 Both edges (when low-level width is measured)
1 1 Both edges (when high-level width is measured)
Bit 3 – 1
MD
033
MD
032
MD
031
Channel n operation mode setting Corresponding function TCR count operation
0 0 0 Interval timer mode
Interval timer /
Square wave output / Divider
function / PWM output (master)
Counting down
0 1 0 Capture mode
Input pulse interval
measurement
Counting up
0 1 1
Event counter mode
External event counter Counting down
1 0 0
One-count mode
Delay counter / One-shot pulse
output / PWM output (slave)
Counting down
1 1 0
Capture & one-count mode
Measurement of high-/low-level
width of input signal
Counting up
Other than
above
Setting prohibited
Bit 0
Operation mode
(Value set by the MDmn3 to MDmn1 bits
(see table above))
MD
030
Setting of count start and interrupt
• Interval timer mode (0, 0, 0)
• Capture mode (0, 1, 0)
0
Timer interrupt is not generated when counting is
started (timer output does not change, either).
1
Timer interrupt is generated when counting is started
(timer output also changes).
• Event counter mode (0, 1, 1)
0
Timer interrupt is not generated when counting is started
(timer output does not change either).
• One-count mode
Note2
(1, 0, 0)
0
Start trigger is invalid during counting operation.
At that time, interrupt is not generated.
1
Start trigger is valid during counting operation
Note 3.
At that time, interrupt is not generated.
• Capture and one-count mode (1, 1, 0)
0
Timer interrupt is not generated when counting is started
(timer output does not change either).
Start trigger is invalid during counting operation.
At that time, interrupt is not generated.