Renesas RL78 - Page 53

RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 53 of 85
Feb. 15, 2017
UART0 Interrupt Priority Level Settings
・Priority level flag registers (PR10L, PR00L)
Set reception/reception error interrupt to level 3 (lowest priority level).
Symbol: PR00H
7 6 5 4 3 2 1 0
STPR01
CSIPR010
IICPR010
TMPR000 SREPR00 1 1
SRPR00
CSIPR001
IICPR001
STPR00
CSIPR000
IICPR000
PPR06
X x 1 x x 1 x x
Symbol: PR10H
7 6 5 4 3 2 1 0
STPR11
CSIPR110
IICPR110
TMPR100 SREPR10 1 1
SRPR10
CSIPR101
IICPR101
STPR10
CSIPR100
IICPR100
PPR16
x x 1 x x 1 x x
Bit 5
SREPR00 SREPR10 Selection of priority level
0 0 Set to level 0 (highest priority level)
0 1 Set to level 1
1 0 Set to level 2
1 1 Set to level 3 (lowest priority level)
Bit 2
SRPR00 SRPR10 Selection of priority level
0 0 Set to level 0 (highest priority level)
0 1 Set to level 1
1 0 Set to level 2
1 1 Set to level 3 (lowest priority level)