Renesas RL78 - Page 54

RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 54 of 85
Feb. 15, 2017
UART0 Channel 1 Error Flag Setting
・Serial flag clear trigger register 01 (SIR01)
Clear all error flags.
Symbol: SIR01
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 FECT
01
PECT
01
OVCT
01
－ － － － － － － － － － － － － 1 1 1
Bit 2
FECT01 Clear trigger for framing error flag of channel n
0 Do not clear
1 Clear SSRmn register FEFmn bit to 0.
Bit 1
PECT01 Clear trigger for parity error flag of channel n
0 Do not clear
1 Clear SSRmn register PEFmn bit to 0.
Bit 0
OVCT01 Clear trigger for overrun error flag of channel n
0 Do not clear
1 Clear SSRmn register OVFmn bit to 0.
UART0 channel 1 Noise Filter ON
・Noise filter enable register 0 (NFEN0)
Set noise filter to ON.
Symbol: NFEN0
7 6 5 4 3 2 1 0
0 0 0 0 0 SNFEN10 0 SNFEN00
x x x x x x x 1
Bit 0
SNFEN00 Enable/disable use of noise filter for RxD0 pin
0 Noise filter OFF
1 Noise filter ON