RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 55 of 85
Feb. 15, 2017
・Serial mode register 01 (SMR01)
Set UART0 channel 1 as follows:
・Operation clock: CK00
・Transfer clock: CK00 divided clock (divided-by-2)
・RxD0 pin valid edge
・Start bit detection: falling edge
・UART mode
・Interrupt source: transfer complete interrupt
Symbol: SMR01
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKS
01
CCS
01
0 0 0 0 0 STS
01
0 SIS
010
1 0 0 MD
012
MD
011
MD
010
0 0 x x x x x 1 x 0 x x x 0 1 0
Bit 15
CKS01 Selection of operation clock (f
MCK
) for channel n
0 Operation clock CKm0 set by SPSm register
1 Operation clock CKm1 set in SPSm register
Bit 14
CCS01 Selection of transfer clock (f
TCLK
) for channel n
0 Divided operation clock f
MCK
specified by CKSmn bit
1 Input clock f
SCK
from SCKp pin (slave transfer in CSI mode)
Bit 8
STS01 Selection of start trigger source
0 Only software trigger is valid (selected for CSI, UART transmission, and simplified I2C)
1 Valid edge of the RxDq pin (selected for UART reception)
Bit 6
SIS01 Control of inversion of receive data level of channel n in UART mode
0
Start bit detected with falling edge.
The input communication data is captured as is.
1
Start bit detected with rising edge.
The input communication data is inverted and captured.
Bit 2 - 1
MD012 MD011 Setting of operation mode for channel n
0 0 CSI mode
0 1 UART mode
1 0 Simplified I
2
C mode
1 1 Setting prohibited
Bit 0
MD010 Selection of interrupt source of channel n
0 Transfer complete interrupt
1 Buffer empty interrupt
(Occurs when data is transferred from the SDRmn register to the shift register.)
UART0 Channel 1 Initialization
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