Renesas RL78 - Page 58

RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 58 of 85
Feb. 15, 2017
・Serial output enable register 0 (SOE0)
Disable output in serial communication operations.
UART0 Out
p
ut Enable Settin
g
・ Serial data register 01 (SDR01)
Set transfer clock to 9600bps.
(9600bps = f
MCK
÷ 208 = 2MHz ÷ 208)
UART0 Channel 1 Baud Rate Setting
・Port mode register (PM5)
Set P55 to input mode.
RxD0 Pin Initialization
Symbol: SDR01
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 x x x x x x x x x
Bit 15-9
SDR01[15:9] Transfer clock setting based on operation clock (f
MCK
) division
0 0 0 0 0 0 0
f
MCK
/2
0 0 0 0 0 0 1
f
MCK
/4
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1 1 0 0 1 1 1 f
MCK
/208 (= f
MCK
/{(103+1)×2})
Symbol: SOE0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOE01 SOE00
x x x x x x x x x x x x x x x 0
Bit 0
SOE00 Serial output enable/disable for channel n
0 Stops output in serial communication operations.
1 Enables output in serial communication operations
Symbol: PM5
7 6 5 4 3 2 1 0
1 PM56 PM55 PM54 PM53 PM52 PM51 1
1 x 1 x x x x 1
Bit 5
PM55 Selection of input/output mode for Pmn pin
0 Output mode (functions as output port, output buffer ON)
1 Input mode (functions as input port, output buffer OFF)