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Renesas RL78 - Page 57

Renesas RL78
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RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 57 of 85
Feb. 15, 2017
Bit 7
DIR01 Setting of data transfer order in CSI and UART modes
0 Inputs/outputs data with MSB first.
1 Inputs/outputs data with LSB first.
Bit 5 - 4
SLC011 SLC010 Setting of stop bit in UART mode
0 0 No stop bit
0 1 Stop bit length = 1 bit
1 0 Stop bit length = 2 bits (mn = 00, 02, 10, 12 only)
1 1 Setting prohibited
Bit 1 - 0
DLS011 DLS 010 Setting of data length in CSI and UART modes
0 1 9-bit data length (stored in bits 0 to 8 of the SDRmn register) (settable in UART mode only)
1 0 7-bit data length (stored in bits 0 to 6 of the SDRmn register)
1 1 8-bit data length (stored in bits 0 to 7 of the SDRmn register)
Other than above Setting prohibited

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