Renesas RL78 - Page 68

RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 68 of 85
Feb. 15, 2017
CPU Clock Chan
g
e Settin
g
・System clock control register (CKC)
Change setting from high-speed to middle-speed on-chip oscillator clock.
Symbol: CKC
7 6 5 4 3 2 1 0
CLS CSS MCS MCM0 0 0 MCS1 MCM1
x x x x x x x 1
Bit 0
MCM1 Operation control of main on-chip oscillator clock (f
OCO
)
0 High-speed on-chip oscillator clock
1 Middle-speed on-chip oscillator clock
TAU0 Channel 1 Timer In
p
ut Settin
g
・Timer input selection register 0 (TIS0)
Set to middle-speed on-chip oscillator clock.
Symbol: TIS0
7 6 5 4 3 2 1 0
0 TIS06 TIS05 TIS04 0 TIS02 TIS01 TIS00
x x x x x 0 1 1
Bit 2 - 0
TIS02 TIS01 TIS00 Selection of timer input used with channel 1
0 0 0 Input signal of timer input pin (TI01)
0 0 1 Event input signal from ELC
0 1 0 Input signal of timer input pin (TI01)
0 1 1 Middle-speed on-chip oscillator clock(f
IM
)
1 0 0 Low-speed on-chip oscillator clock (fIL)
1 0 1 Subsystem clock (fSUB)
Other than above Setting prohibited