Renesas RL78 - Page 69

RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 69 of 85
Feb. 15, 2017
・Timer mode register 01 (TMR01)
Set to valid edge of input signal.
TAU0 Channel 1 Count Clock Setting
・Timer data register 01 (TDR01)
Set TAU0 channel 1 compare value to 1295H.
TAU0 Channel 1 Compare Value Setting
Symbol: TMR01
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKS
011
CKS
010
0 CCS
01
SPLIT
01
STS
012
STS
011
STS
010
CIS
011
CIS
010
0 0 MD
013
MD
012
MD
011
MD
010
x x x 1 x x x x x x x x x x x x
Bit 12
CCS01 Selection of count clock (f
TCLK
) for channel n
0 Operation clock (f
MCK
) specified by CKSmn0 and CKSmn1 bits
1 Valid edge of input signal from TImn pin.
Symbol: TDR01
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1