Renesas RZ/A2M - Page 39

RZ/A2M SUB Board RTK79210XXB00000BE 2. Function specifications
R20UT4398EJ0100 Rev.1.00 2-21
2018.10.11
Table 2.3.4 Bus State Controller Settings (SDRAM read/write) (1)
User region
Target device
Bus state controller settings
CS3
IS42S16320F-7TL
■ CS3 space bus control register (CS3BCR)
・Initial setting: H'36DB 0C00
・Recommended setting: H'0000 4C00
- Memory specification:
TYPE[2:0] = B'100; SDRAM
- Data bus width specification:
BSZ[1:0] = B'10; 16 bit bus width
■ CS3 space wait control register (CS3WCR)
・Initial setting：H'0000 0500
・Recommended setting: H'0000 2D13
- Number of precharge completion wait cycles:
WTRP[1:0] = B'01; 1 cycle
- Number of ACTV command → READ (A) /WRIT (A) command interval wait
cycles:
WTRCD[1:0] = B'11; 3 cycle
- Area 3CAS latency:
A3CL[1:0] = B'10; 3 cycle
- Number of precharge start wait cycles:
TRWL[1:0] = B'10; 2 cycle
- Number of REF command/ self refresh cancel →ACTV/REF/MRS command
interval idle cycles:
WTRC[1:0] = B'11; 8 cycle
■ SDRAM control register (SDCR)
・Initial setting: H'0000 0000
・Recommended setting: H'0012 0812
- Refresh control:
RFSH = 1; refresh
- Refresh mode:
RMODE = 0; carry out auto refresh
- Bank active mode:
BACTV = 0; Auto-precharge mode
- Number of area 3 row address bits:
A3ROW[1:0] = B'10; 13 bit
- Number of area 3 column address bits:
A3COL[1:0] = B'10; 10 bit
■ Refresh timer control/status register (RTCSR)
・Initial setting: H'0000 0000
・Recommended setting: H'A55A 0010
- clock selection:
CKS[2:0] = B'010; CKIO/16
- Number of refresh:
RRC[2:0] = B'000; 1 time
■ Refresh time constant register (RTCOR)
・Initial setting: H'0000 0000
・Recommended setting: H'A55A 0040
1 cycle＝121 nsec (132 MHz/16 = 8.25 MHz)
Required refresh interval of this SDRAM: 7.8125 sec / time
7.8125 sec / 121 nsec = 64 (H'40) cycle/ number of refresh