Rockchip RK3566 EVB2 - MIPI;LVDS Output Interface; MIPI DSI;LVDS TX0 Interface

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33
CAMERA1_PDN
34
MIPI_RST1
35
GND
36
MIPI_MCLK1
37
GND
38
MIPI_CSI_RX_CLK1N_CON
39
MIPI_CSI_RX_CLK1P_CON
40
GND
3.13 MIPI/LVDS Output Interface
The MIPI/LVDS video output interface connected a vertical connector with a pitch of 1mm, and MIPI
DSI/LVDS_TX0 is the default display interface.
Figure 3-14 MIPI DSI/LVDS_TX0 and MIPI DSI _TX1 Video Input Interface
The MIPI DSI/LVDS_TX0 interface signal sequence is as follows:
Table 3-2 MIPI DSI/LVDS_TX0 Signal Definition
1
GND
2
MIPI_DSI_TX0_D0N
3
MIPI_DSI_TX0_D0P
4
GND
5
MIPI_DSI_TX0_D1N
6
MIPI_DSI_TX0_D1P
7
GND
8
MIPI_DSI_TX0_CLKN
9
MIPI_DSI_TX0_CLKP
10
GND
11
MIPI_DSI_TX0_D2N
12
MIPI_DSI_TX0_D2P
13
GND
14
MIPI_DSI_TX0_D3N
15
MIPI_DSI_TX0_D3P
16
GND