Rockchip RK3566 EVB2 - MIPI DSI TX1 Interface

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17
LCD0_BL
18
NC
19
VCC3V3_LCD0
20
LCD0_RST
21
LCD0_ID
22
LCD0_PWREN_H
23
I2C_SCL_TP0
24
ISC_SDA_TP0
25
TP_INT
26
TP_RST
27
GND
28
VCC5V0_LCD_0
29
VCC5V0_LCD_0
30
VCC5V0_LCD_0
The MIPI DSI_TX1 interface signal sequence is as follows:
Table 3-3 MIPI DSI _TX1 Signal Definition
1
GND
2
MIPI_DSI_TX1_D0N
3
MIPI_DSI_TX1_D0P
4
GND
5
MIPI_DSI_TX1_D1N
6
MIPI_DSI_TX1_D1P
7
GND
8
MIPI_DSI_TX1_CLKN
9
MIPI_DSI_TX1_CLKP
10
GND
11
MIPI_DSI_TX1_D2N
12
MIPI_DSI_TX1_D2P
13
GND
14
MIPI_DSI_TX1_D3N
15
MIPI_DSI_TX1_D3P
16
GND
17
LCD1_BL_PWM
18
NC
19
VCC3V3_LCD1
20
LCD1_RST
21
LCD1_ID
22
LCD1_PWREN_H
23
I2C_SCL_TP1
24
ISC_SDA_TP1
25
TP1_INT
26
TP1_RST
27
GND
28
VCC5V0_LCD_1