Chapter 5 – SPI Protocol
Revision 2.2 SD Card Product Manual
© 2004 SanDisk Corporation 5-17 12/08/04
Identifier Inc in Resp. Type Value Description Clear
Condi-
tion
received
5.22 Card Registers
In SPI Mode, only the OCR, CSD and CID registers are accessible. Their format is
identical to their format in the SD Card mode. However, a few fields are irrelevant in SPI
mode.
5.23 SPI Bus Timing Diagrams
All timing diagrams use the schematics and abbreviations listed in Table 5-4.
Table 5-4 SPI Bus Timing Abbreviations
Symbol Definition
H Signal is high (logical 1)
L Signal is low (logical 0)
X Don’t care
Z High impedance state (-> = 1)
bullet Repeater
Busy Busy token
Command Command token
Response Response token
Data block Data token
All timing values are defined in Table 5-4. The host must keep the clock running for at least
NCR clock cycles after the card response is received. This restriction applied to command
and data response tokens.
5.23.1 Command and Response
Host Command to Card Response—Card is Ready
5.23.2 Host Command to Card Response--Card is Busy
The following timing diagram describes the command response transaction for commands
when the card responses with the R1b response type (e.g., SET_WRITE_PROT and
ERASE).
When the card is signaling busy, the host may de-select it (by raising the CS) at any time.
The card will release the DataOut line, one clock after the CS going high. To check if the
card is still busy, it needs to be re-selected by asserting (set to low) the CS signal. The card
will resume busy signal (pulling DataOut low) one clock after the falling edge of CS.
X X H H H H
Z Z Z H H H H
H H L L L *******************
6 byte cmd H H H H H ***************
H H H H H********
H H H H X X X
1 or 2 byte response H H H H H Z Z
L L L L H H H
N
CS
N
EC
N
CR
CS
Data In
Data Out
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