Chapter 4 – SD Card Protocol Description
Revision 2.2 SanDisk SD Card Product Manual
© 2004 SanDisk Corporation 4-44 12/08/04
Multiple Block Read
In multiple-block read mode, the card sends a continuous flow of data blocks following the
initial host read command. The data flow is terminated by a stop transmission command,
CMD12. The Timing of Multiple Block Read Command timing diagram describes the
timing of the data blocks, and the Timing of Stop Command (CMD12, Data Transfer Mode)
timing diagram describes the response to a stop command. The data transmission stops two
clock cycles after the end bit of the stop command.
Timing of Multiple Block Read Command
Timing of Stop Command (CMD12, Data Transfer Mode)
4.12 Data Write
Single Block Write
The host selects one card for data write operation by CMD7. The host sets the valid block
length for block-oriented data transfer by CMD16.
The basic bus timing for a write operation is shown in the Block Write Command timing
diagram. The sequence starts with a single block write command, CMD24 that determines
(in the argument field) the start address. The card responds on the CMD line, and the data
transfer from the host starts N
WR
clock cycles after the card response was received.
The data is suffixed with CRC check bits to allow the card to check it for transmission
errors. The card sends back the CRC check result as a CRC status token on the DAT0 line.
In the case of transmission error the card sends a negative CRC status (‘101’). In the case
of non-erroneous transmission the card sends a positive CRC status (‘010’) and starts the
data programming procedure. When a flash programming error occurs the card will ignore
all further data blocks. In this case no CRC response will be sent to the host and, therefore,
there will not be CRC start bit on the bus and the three CRC status bits will read (‘111‘).
Block Write Command Timing
CMD S T E Z * P S T
Response
CRC EZ P
DAT
Z Z **** Z Z **********Z P S D DZ Z Z Z P D *****
Z PZ P P PP P PPP P P P P
N
CR
Cycles
D E P ********** P DDS D D D
Content
CRC
Content
Host Command
N
AC
CyclesN
AC
Cycles
Read Data
Read Data
CMD S T E Z *** P S TZ P
N
CR
Cycles
Content
CRC
Host Command
Content ECRC
D D D ******** D D D E Z Z **********
Response
DAT
CMD E Z
Busy
CRC E Z Z P P PP P PPP P
N
CR
Card Response
Content
Host
Command
Write Data CRC Status
Z
P * P S ******************T
DAT0
Z Z ****
SZ Z Z E S
E Z
***Z Z Z Z P*P Content CRC E Z Z S Status L*L
DAT1-3
Z Z ****
SZ Z Z
X X
X Z
***Z Z Z Z P*P Content CRC E Z Z X
X X X
X X
N
WR
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