Sequential PROPHET-600 - Non-Volatile Ram Protection and Power Detection

DAC. TB304 sends seven DMUX address lines, and receives the outputs of the ADC
CPR and tune comparator (TUNE CPR). The synth switch commands, and a +5V supply
line go out over TB305. And. as mentioned. Vmux comes in separately from PCB 2,
through P401. This makes for very-low noise in the ADC circuit.
The main power supply on PCB 3 generates ♦ /- 5V and ♦ /- 15V. Only +5 goes to PCB1,
for digital. PCB 1 has a separate *5V regulator for analog. The feed voltage to this
regulator comes via PCB 4. PCB 4 receives -5V and +/-15V from PCB 3.
2-2 NON-VOLATILE RAM PROTECTION AND POWER DETECTION
We begin the circuitry discussion from the condition of power off. To maintain the
integrity of the sound programs stored in RAM a constant voltage to the RAMs is
required and the CPU must be disabled during power-on/off transitions. See SD600-3,
sheet "C" in the document section. Battery BT301 (located on the schematic near the
78L05 regulator) supplies 2.9V, which is dropped to 2.2V by D310. This Vnv (nv=non-
volatile) powers U313 and U316, the 6116LP 2K x 8 bit static RAMs which hold the
programs and sequences. Two logic packages, which operate the power detector and
RAM protect circuit, and capacitor C312 also receive Vnv.
One of these packages is in the power detector circuit. U308-1 is high because both
inputs are low (since power is off). This high is applied directly to U308-9, and to
U308-8 through D3I2. U308-10 -RESET is therefore low (true). The CPU (U307-26)
will remain reset until this line goes high (false). It also (via the line to sheet D) holds
programmed switch latch U331 (-CS03) clear. This helps prevent random squawks
which result because the switches connected to this latch momentarily close on power-
up.
Inverting the -RESET signal, U308-13 is high, that is, -PWR ON is false. In the RAM
protect circuit, this high disables RAM decoder gates U315-6 and -8 (the second nv
logic package). The two RAM -CE (chip enable) lines are high, preventing alteration of
memory.
When power is switched on regulator U332 through D309 simply overrides the battery
voltage, providing standard operating voltage for the NV RAMs and two logic
packages. D308 biases the common terminal of the regulator 0.6V above ground. This
sets a regulator output of + 5.6V. But D309 drops 0.6V, resulting in a net +5V supply.
D310 prevents this voltage from charging the (not rechargable) lithium battery. U301,
the main +5V regulator, comes to life and starts the system clock (discussed below).
Meanwhile, in the power detect circuit, D311 and D316 form their own full-wave
rectifier which presents the first peak across filter C308/R335 and divider R305/D315.
When the divided voltage exceeds the 6V Zener by the CMOS high threshold of about
3.5V, in other words 9.5V, U308-1 goes low. Input U308-9 goes low immediately. Pin 8,
however, is held high by the (Vnv) charge on C312, which begins to discharge through
R307. After about one second, pin 8 falls low enough so U308-10 -RESET can go high,
enabling the CPU and switch latch. U308-13 -PWR ON goes low, enabling RAM access
through the decoder gates.
TM600A 7/83
2-5