Sequential PROPHET-600 - SYNTHESIZER CONTROLS

When power is switched off the falling voltage causes the power detector to
immediately pull -RESET low, stopping the CPU even though the system clock may
still be running. Then the false -PWR ON signal again disables any RAM access. This
prevents random instructions from being performed during power-down which could
alter RAM contents.
2-3 SYSTEM CLOCK
The system clock is generated by Y301 8-MHz crystal and two inverters of U305 in a
simple RC oscillator circuit.
(The miscellaneous gates U305-2, U311-3, and U312-3 only allow the injection of test
clock signals at the factory. Pulling U311-1 low disables the 8 MHz clock. The test
clock is then injected at U312-2.)
Divider U306 provides 4 MHz for the Z-80A. In addition, two slower clocks drive the
interrupt system, Tune system, and MIDI serial interface. The 2 MHz output drives
U320-9 interrupt clock and U320-15 Tune Total Time counter. The 500 kHz output
drives 14U319 NMI CLR flip-flop and U323 UART. The purpose of these clock signals
will be discussed in each circuit.
2-4 MICROCOMPUTER
With the clock running and -RESET high, the CPU's program counter is initialized to
memory address 0000H (Hex). All address lines A0-A15 will be low. AO through A12
define the first memory location in EPROM U310. But this is not enough to read the
instruction in this location because many memory and I/O devices share these address
lines. A signal is needed to differentiate the EPROM from the RAMs and other
devices. This signal is generated by U309 Memory Address Decoder. With A12 through
A14 low, and -MREQ input low—which indicates that the address bus holds a valid
memory address—to -G2A the decoder output -Y0 goes low. -RFSH indicates that the
address bus holds a valid refresh address. Applied to Gl, this signal is used to disable
the decoder whenever this is the case. The -Y0 output nors its way through U311-6,
becoming the -ROM signal which actually enables (-OE) the output of the EPROM.
(Although using the 2764 -CE input would reduce power consumption, -OE was used for
maximum memory access speed.) The EPROM places the instruction from location 0
on the data bus (D0-D7), from which it is retrieved by the CPU's instruction register.
Any program address in the first 4K bytes of memory (0000H-0FFFH) will be selected
by -Y0. Addresses in the next 4K (1000H-1FFFH) will set A12, therefore -Y1 will
appear. Either signal produces the -ROM strobe through U311-6.
All EPROM operations are memory-read. When the CPU needs to write to or read one
of the RAMs, the decoder selects -RAMI for addresses 2000H-27FFH or -RAM2 for
3000H-37FFH. These strobes are gated to the RAMs by U315-6 and -8 only if power is
on (see above). The transfer of data from CPU to RAM is enabled by the -WR (write)
line being true. The opposite direction, from RAM to CPU, is enabled by -RD (read).
2-6 TM600A 7/83