Sequential PROPHET-600 - Computer Troubleshooting

Also from the memory address decoder, the -DAC line is combined with and AO to
produce a strobe for the DAC LO and HI output latches at memory addresses 4000H
and 4001H, respectively. Memory-mapping the DAC provides a fast and easy way to
send it the data which it converts to the various svnthesizer CVs.
V: 1 V/div
H: .1 us/div
Figure 2-2
ADDRESS AO
The uppermost memory-mapped device is U323 UART, which has two control registers
that need to be accessed. These are decoded somewhat differently from the other
memory locations. The combination of AO, A13, A14, A15 define 6000H and 6001H as
write address (A15 low), and E000H/E001H as the read address (A15 high). (The 40 nsec
delay applied to -RD which is gated through U314-8 times the clock pulse needed to
interface this 6800-system part to the Z-80A.)
Input/output interface follows similar principles as memory interface. The address
lines define ports which are validated by -IORQ (instead of -MREQ). -IORQ (CPU pin
20) connects between U320 8253 timer, an input port decoder made from a few gates,
and U322 output decoder which is similar to the memory decoder. With regard to I/O,
-RD true defines an input operation, typically from data bus drivers which hold data
from the keyboard or control panel (that, is ADC). -WR defines an output to a latch or
register. For example the timer is I/O mapped because it is too slow to run memory-
mapped at this speed. (I/O inserts an extra 250 ns wait state.)
2-5 COMPUTER TROUBLESHOOTING
For troubleshooting, it should be emphasized that most computer malfunctions are
caused by failures of devices connected to the data bus. A shorted latch input (for
instance) can prevent an entire data line from achieving the minimum voltage needed
to signify a high signal. Shorts between data lines will also confuse the computer
terribly.
TM600A 7/83
2-7