Sequential PROPHET-600 - Page 40

precisely-measures oscillator and filter frequencies over a nine-octave range, and
learns the exact CVs required to produce perfectly-tuned octaves. The differences
between the theoretical and actual CVs which produce specific intervals are called
tuning "biases." When playing, these biases are independently recalculated for each
note and each oscillator, so that all twelve oscillators remain in tune throughout their
range. In other words the computer measures the oscillator error at octaves, then
while you play averages the error and corrects the note to which that oscillator
happens to be assigned.
Unlike the earlier Prophets, the -600 contains no Tune Multiplexer. Instead, for tuning,
the Final VCA is switched off and the computer selects the oscillators and filters
which drive U466 TUNE COMPARATOR (see Sheet E). C4197 prevents oscillations.
The comparator output crosses back to PCB 3 for counting by the Tune circuit (see
sheet D).
The squared-up oscillator or filter pulses drive a flip flop, which clocks a
programmable one shot which in turn gates an event counter. Frequency is measured in
terms of h-us events. There is a reference number of events (stored in EPROM) which
will be produced by counting for one cycle at a specific octave, or for two cycles at an
octave above that, or for four cycles at two octaves up, and so on. At each octave, the
oscillator CV is adjusted by successive approximation until the total time count equals
the reference count. When it does, the oscillator is in tune. It will take slightly more
or less than exactly tt-volt to tune exactly one octave higher. This small but
significant voltage difference is the bias which is averaged over the individual
semitones.
For example, to tune OSC 1A to 261 Hz, the CPU first programs the Cycle Counter to
count one cycle. The MSB of the DAC is set and this CV is applied to OSC 1A. OSC
begins to generate a pitch in the upper middle of its range.
U326-15 latches out the gate (G) signal which enables the Cycle Counter. Then it
outputs the -FFP pulse which by presetting Q, forces -Q low. This we call a "fake"
clock pulse which is actually required for the Cycle Counter to begin its count
accurately (due to the design of the counter itself). The FF is then cleared by the -FF
CL bit, in preparation for the oscillator or filter pulse. The FF status is monitored by
U325 MISC DRIVER.
FFD goes high, gating the oscillator pulse which is inverted through -Q. When the
Cycle Counter receives the first low edge (after the fake clock), its output (pin 17)
goes low. (Also monitored by U325.) This signal is inverted, enabling the Total Time
counter, which begins to increment at the 2 MHz rate.
Since the Cycle Counter has been progammed for a terminal count of one, when it
receives the next low edge, pin 17 goes high, stopping the Total Time counter. The
Total Time register now holds the number of 2-MHz pulses equivalent to one oscillator
cycle. The CPU sees that this specific total time count is way above the reference.
This is because setting the MSB happens to drive the oscillator about an octave above
the first-measured frequency of 261 Hz. So the computer turns off the MSB, sets the
next significant digit, and measures the resulting count. It continues in this manner,
setting each bit which does not cause the oscillator to overshoot its reference count.
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TM600A 7/83