Sharp LC-52XS1E - Page 71

LC-52XS1E/RU/LC-65XS1E/RU
5 – 12
16.IC6951 (VHiYDA147SZ-1Y)
This is a digital amplifier. The 52” and 65” models are driven with 15W.
AUDIO POWER AMPLIFIER
17.IC7103 (RH-iXC582WJQZQ)
This is an FPGA, which receives the 10-bit LVDS signal from IC6201, implements the color gamut conversion and skin color correction, and out-
puts via the 10-bit RGBs of LVTTL. Also, while the I2S signal is input from IC6102, it implements the audio delay processing for the delay of the
pictures generated on the LCD TCON+A3C and subsequent PWBs.
18.IC7502 (VHiTLVD1023-1Q)
This is an LVDS Tx, which converts the 10-bit RGBs of LVTTL from IC7103 into the LVDS signals.
LVDS Transmitter.
27 AINL I Analog Input Left Channel.
28 AINR I Analog Input Right Channel.
29 TEST12 I Reserved for Internal Use. Connect to DGND.
30 TEST13 I Reserved for Internal Use. Connect to DGND.
31, 32, 33 OUTR+ O Output of High Power Transistors, Right Channel Positive Polarity.
34, 35, 36 OUTR- O Output of High Power Transistors, Right Channel Negative Polarity.
37, 38, 47,
48
PGND - Power Ground for High Power Transistors. Internally connected to exposed pad (ePAD).
39, 40, 41,
42, 43, 44,
45, 46
PVDD - Positive Power Supply for High Power Transistors.
Pin No. Pin Name I/O Pin Function
1, 2, 12, 25,
35, 36
NC - No Connection
3 PVDDREG - The power supply terminal for regulators (PVDD).
4 AVDD - The output terminal for 3.3V regulators
5 INLP I Analog input terminal (Lch+)
6 INLM I Analog input terminal (Lch-)
7 VREF - VREF Terminal
8 INRM I Analog input terminal (Rch-)
9 INRP I Analog input terminal (Rch+)
10 AVSS - Analog ground terminal
11 PLIMIT I Power limit setting terminal
13, 14 PVDDPR - The power supply terminal for a digital amplifier output (Rch+)
15, 16, 17 OUTPR O Digital amplifier output terminal (Rch+)
18, 19 PVSSR - The ground terminal for a digital amplifier output (Rch)
20, 21, 22 OUTMR O Digital amplifier output terminal (Rch-)
23, 24 PVDDMR - The power supply terminal for a digital amplifier output (Rch-)
26 SLEEPN I Sleep control terminal
27 PROTN O Error flag output terminal
28 MUTEN I Mute control terminal
29 CKOUT O The clock output terminal for a synchronization
30 CKIN I External clock input terminal
31 NCDRC0 I Non clip / DRC1/DRC2 mode-select terminal 0
32 NCDRC1 I Non clip / DRC1/DRC2 mode-select terminal 1
33 GAIN0 I GAIN setting terminal 0
34 GAIN1 I GAIN setting terminal 1
37, 38 PVDDML - The power supply terminal for a digital amplifier output (Lch-)
39, 40, 41 OUTML O Digital amplifier output terminal (Lch-)
42, 43 PVSSL - The ground terminal for a digital amplifier output (Lch)
44, 45, 46 OUTPL O Digital amplifier output terminal (Lch+)
47, 48 PVDDPL - The power supply terminal for a digital amplifier output (Lch+)
Pin No. Pin Name I/O Pin Function