Siemens 7SR224 - Figure 4.5-1 Sequence Diagram: Quick Logic PU;DO Timers (Counter Reset Mode Off)

7SR224 Argus Description of Operation
P.U. DE
L
AY
D.O. DELAY
T
Counter Value 1 2
Increment
Counter
Equation Output 1
0 101
For Counter Target = 2
En = 1
Equation n P.U. DELAY D.O. DELAY Counter En = 1
Counter
= Target Value
Figure 4.5-1 Sequence Diagram: Quick Logic PU/DO Timers (Counter Reset Mode Off)
When the count value = En Counter Target the output of the counter (En) = 1 and this value is held until the
initiating conditions are removed when En is instantaneously reset.
The output of En is assigned in the OUTPUT CONFIG>OUTPUT MATRIX menu where it can be programmed to
any binary output (O), LED (L) or Virtual Input/Output (V) combination.
Protection functions can be used in Quick Logic by mapping them to a Virtual Input / Output.
Refer to Section 7 – Applications Guide for examples of Logic schemes.
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