SimCom SIM7600V-H

Smart Machine Smart Decision
SIM7600V-H_User Manual_V1.00 2018-02-24
32
Figure 22: Module to EXT codec timing
Table 15: PCM Timing Parameters
Parameter
Description
Min.
Typ.
Max.
Unit
T(sync)
PCM_SYNC cycle time
–
125
–
μs
T(synch)
PCM_SYNC high level time
–
488
–
ns
T(syncl)
PCM_SYNC low level time
–
124.5
–
μs
T(clk)
PCM_CLK cycle time
–
488
–
ns
T(clkh)
PCM_CLK high level time
–
244
–
ns
T(clkl)
PCM_CLK low level time
–
244
–
ns
T(susync)
PCM_SYNC setup time high before falling edge of
PCM_CLK
–
122
–
ns
T(hsync)
PCM_SYNC hold time after falling edge of
PCM_CLK
–
366
–
ns
T(sudin)
PCM_IN setup time before falling edge of
PCM_CLK
60
–
–
ns
T(hdin)
PCM_IN hold time after falling edge of PCM_CLK
60
–
–
ns
T(pdout)
Delay from PCM_CLK rising to PCM_OUT valid
–
–
60
ns
T(zdout)
Delay from PCM_CLK falling to PCM_OUT
HIGH-Z
–
–
60
ns
3.6.2 PCM Application Guide
The following figure shows the external codec reference design.