Sony DP-IF5000 - 5 Diagrams; Block Diagram -Processor Section; Block Diagram -Transmitter Section

– 9 – – 10 – – 11 –
DP-IF5000
5-1. BLOCK DIAGRAM — PROCESSOR SECTION —
– 12 –
SECTION 5
DIAGRAMS
5-2. BLOCK DIAGRAM — TRANSMITTER SECTION —
61 80
SPFRK
SDI0
SDI1
SCKR
SCKT
WSR
WST
MISO/SDA
BUSY
SI
SCK/SCL
SDB
DIGITAL
FRONT LR
79
SBC
SDO0
VCCA
VCCD
REAR LR
BCK 64fs
L/R 1fs
95
91
SCKB
SCKA
95
92
WSB
WSA
B+
(+5V)
9
10
12
13
5
4
1
2
8
11
6
3
66
SCKIN
MCK 256fs
34
SO
58
GPIO0
89
SI
B+
(+5V)
5
4
2
1
13
12
6
3
11
NAND
IC303
AC-3/PROLOGIC
SURROUND DECODER
IC301
LOGIC 3D
PROCESSOR
IC302
NAND
IC304
SO1
87
SCK
82
RESET
3
SS
64
70
XT1
VCCA
SCK1
CLOCK 12M
51
56 47
70
57
49
55
50
35
41
26
6
•
17
B+
(+5V)
VCCS
40
•
48
B+
(+5V)
VCCQ
9
•
28
•
53
B+
(+5V)
B+
(+5V)
VCCP
30
HREQ
43
CS
42
RESET
36
GPIO3
73
GPIO2
74
GPIO1
75
GPIO0
76
EXTAL
27
B+
(+5V)
P20(SI1)
57
P01
37
P21(SO1)
58
P22(SCK1)
59
P12
49
P11
X1
X2
X1
X2
48
P64
SI1
S01
SCK1
RESET
SSZ11
31
P65
32
P66
33
P67
34
P17
54
P10
47
P24(BUSY)
61
P40
10
P41
11
P42
12
P43
13
P44
14
P50
18
P51
19
P52
20
P27
64
P26
P16
P15
P57
RESET
63
RESET
POWER
SELECT
MODE
EFFECT
DEMO
LEDEN
EN
LAT
RES
SCK
MUTE
POWER A
POWER B
RESET
SIN O2
O3
O4
O5
O6
O8
O1
LEDLAT
LEDRES
SCK0
SO0
SW
BLOCK
SW1-5
DISPLAY
LED DRIVE
IC206
15
3
2
13
14
8
9
10
11
12
7
5
RES
SCK
SIN
SO
LAT
O2
O3
O4
O5
O6
O7
O1
DISPLAY
LED DRIVE
IC205
13
14
15
3
EN
CLK10
RST
BCKIN
LRCK
LR DATA
2
4
8
9
10
11
12
7
6
O8
5
TRANSMITTER
SECTION
2
TRANSMITTER
SECTION
1
DISPLAY
LED DRIVE
D201-208
DISPLAY
LED
D209-214,216
12 13
1 2
5
3
4
11
8 41
V
DD
40
AV
DD
55
42
52
26
35
539
INVERTER
IC203(1/2)
10 6
9
CMOS LOGIC
IC201
CLOCK
Q1
Q3
X201
12.288MHz
6
10
INVERTER
IC203(2/2)
B+
(+5V)
TRANSMITTER
SECTION
3
8319
SDA
D OUT
B+
(+3.3V)
6
•
12
•
17
•
30
•
35
•
45
•
55
•
59
•
67
•
81
•
84
•
93
VDD
B+
(+3.3V)
DIGITAL
AUDIO
INTERFACE
(1/2)
DECIMATION
FILTER
DELTA
SIGMA
MODULATOR
ANALOG
FRONT END
ANALOG
FRONT END
+
–
+
–
V IN L
V IN R
1
6
19
A/D CONVERTER
IC102 (1/2)
+
–
+
–
3
2
6
5
1
6
LINE AMP
IC101
ATT SW
Q101
ATT SW
Q102
B+
(+9V)
SW101
ATT
0dB
–6dB
ANALOG L
ANALOG R
L
R
LINE INPUT
J101
–1
–2
1
3
OUT
VCC
OPTICAL
RECEIVER
MODULE
IC305
DIGITAL IN
B+
(+5V)
DIGITAL
: DIGITAL
Signal path
PROGRAM,
SYSTEM
CONTROL
IC105
: ANALOG
PROCESSOR
SECTION
1
DIGITAL
AUDIO
INTERFACE
(
2/2
)
+
–
+
–
LR DATA
PROCESSOR
SECTION
2
LRCK
BCK IN
CLK10
RST
INTERPOLATION
FILTER
DELTA SIGMA
MODULATION
CLK/OSC
MANAGER
RESET
BIAS
LPF
&
BUFFER
LPF
&
BUFFER
V OUT L
V COM
V OUT R
BINAURAL L
BINAURAL R
+
18
16
17
22
28
11
12
15
D/A CONVERTER
IC102
(
2/2
)
3
2
1
7
5
6
+
–
+
–
5
6
7
1
3
2
MUTE
Q31
MUTE
Q32
MUTE
Q901
MUTE
Q902
MUTING
SW
Q33,34
PROCESSOR
SECTION
3
MUTE
POWER A
POWER B
RESET
BINAURAL R
B+ (SW+5V)
BINAURAL L
13
9
1
7
RV901
PHONES
LEVEL
HEADPHONES
AMP
IC901
J901
PHONES
+9V
REG
IC805
B+
(+9V)
LF801
B+
(SW+9V)
B+
(SW+5V)
B+
(+5V)
+9V
REG
IC804
SW+9V
REG
Q803
RESET
IC204
+5V
REG
IC801
+5V
REG
IC802
+3.3V
REG
IC803
B+
(+3.3V)
J801
DC IN 9V
AFC
IC1
AUDIO AMP
IC103
6
4
2
6
4
2
L51
FREQUENCY
(L-CH)
RV51
RF LEVEL
(L-CH)
2.3MHz OSC
COIL
L1
FREQUENCY
(R-CH)
2.8MHz OSC
COIL
OSC
Q51
OSC
Q1
BUFFER
Q52
LED
DRIVE
Q301,351
LED
DRIVE
Q302,352
RV1
RF LEVEL
(R-CH)
BUFFER
Q2
REG
SWITCH
Q35, 36
B+
(+9V)
B+
(+9V)
INFRARED
EMITTER
D301-304
INFRARED
EMITTER
D305-308
D1
D51
DIN
• Signal path
: DIGITAL
: ANALOG
: RF
-1
L
-2
R