– 34 –
SECTION 5
DIAGRAMS
5-1. EXPLANATION OF IC TERMINALS
IC402 µPD17072GB-556-1A7 (PLL SYNTHESIZER CONTROL)
Pin No. Pin name I/O Description
1 ROD/BAR O ROD/BAR antenna select output. “H” : BAR, “L” : ROD
2 AM/FM O AM/FM select output. “H” : AM, “L” : FM
3 ENV/PSN O ENV/PSN select output. “H” : ENV, “L” : PSN
4 SSB/SYNC O SSB/SYNC select output. “H” : SSBR, “L” : SYNC
5 L/U O USB/LSB select output.
6 BAND0 O Meter band select output.
7 BAND1 O Meter band select output.
8 BAND2 O Meter band select output.
9 BAND3 O Meter band select output.
10 – 13 ––––– – Not used (OPEN).
14 DA0 I/O DA signal in/out terminal.
15 DA1 I/O DA signal in/out terminal.
16 DA2 I/O DA signal in/out terminal.
17 DA3 I/O DA signal in/out terminal.
18 GND – Ground terminal.
19 EO O PLL charge pump output.
20 VCOL I MF, HF input terminal.
21 VCOH I VHF input terminal.
22 REGO O Regurator output for PLL.
23 VDD – Power supply terminal.
24 XOUT O Osillator output terminal (75kHz).
25 XIN I Osillator input terminal (75kHz).
26 REG1 O Regurator output for oscillator.
27 – 49 ––––– – Not used (OPEN).
50 CE I Chip enable input.
51 REQ I PLL request signal input.
52 PLL-CTL O PLL control output.
53 UNLOCK O PLL unlock signal output.
54 ACK O Clock signal ouput for system control (IC501).
55 SCK O Clock signal ouput for sub system control (IC502).
56 SI I Data signal input for sub system control (IC502).
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TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
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