Sony RCD-W1 - CD-R Section Block Diagrams (2;2); CD-R Section Block Diagram (Continued)

RCD-W1
26 26
– CD-R SECTION (2/2) –
OUT VCC
CTRL
163 EF M
201 BS
203 RP
198 TE
197 FE
191 RX
192 TX
EFM
BS
RP
TE
FE
RX
TX
34MCLK
207 FA O
208 TA O
SLO
DMD
183 EFM1
184 EFM2
185 EFM3
180 WRSMP
181 RESAMP1
182 RESAMP2
177
186
EFCK
142
ROPC1
LDON
204
FG
194
CE
166
TEBC
179
104 105
WGATE
FEFS
FAO
TAO
SLO
DMD
EFM1
EFM2
EFM3
WRSMP
RESAMP1
RESAMP2
EFCK
ROPC1
LDON
FG
CE
TEBC
WGATE
FEFS
8
3
2
7
EFM
69HRD#
70
146
HWR#
DOUT
62HA1
60HA0
59HA2
57CS1FX
56CS3FX
DIORB
DIOWB
BUS DA1
BUS DA0
BUS DA2
CSB1
CSB3
30RCASH#
31RCASL#
38RRAS#
37RWE#
36
97 94 95
ROE#
/WE
OE
/CS
URD# UAD0 I UAD7 UA0 I UA8
96-103
11-13,15-191-10,21,23-26
RD0
I
RD15
I/O0
I
I/O15
I/O0
I
I/O7
A0
I
A14
A0
I
A9
RA0
I
RAD9
32,33,29-24,
21-14
HD0
I
HD15
72,73,76-82,
85-91
52-48,
45-81
31 /UCAS
32 /LCAS
15 /RAS
14 /WE
30 /DE
HRST# PRST#
27
22
20
33-4013-27
30
31
32
89
88
87
72
73
OUTDATA1 <0>
I
OUTDATA1 <7>
RAM_DATA <0>
I
RAM_DATA <7>
RAM_ADDRESS <0>
I
RAM_ADDRESS <14>
OUTDATA2 <0>
I
OUTDATA2 <7>
DIOWB
DIORB
BUS_DA <1>
BUS_DA <0>
BUS_DA <2>
CSB1
CSB3
DIOWB
DIORB
BUS_DA1
BUS_DA0
BUS_DA2
CSB1
CSB3
RAM_WEB
RAM_OEB
RAM_CSB
70
71
49
42
41
43
44
46
45
59
51
60
62
65
1 2
4
1
2
61
48
13
4
12
14
17
18
16
21
26
2
1
27
28
2-5,7-10,
35-38,40-43
1-10,
80-75
18-21,
24-29
130-122
UWR#
106 107
UCS0#
10
OPT_S
M_S
9,11
9,10,11
UCS1#
110 111
URDY UINT0#
112 113
UINT1# SDINT#
/URD
UAD0
I
UAD7
UA0
I
UA8
27-34
70 71
5458 88 89 17
36-43,45
/UHWR
SLDFG SBRK SPNFG
98
SPNON
85
SLDMOVE
2
ATIP/EFM
25
TRAY_MUTE
26
3
9553
66
REC_TXD
REC_RXD
REC_CLK
FWE_ON
FWE
FWMD2
BTS_RXD
BTS_TXD
12
14
16
75
15
9
10
ACT_MUTE
SLDFG SBRK SPNFG SPNON SLDMOVE ATIP/EFM TRAY_MUTE ACT_MUTE
46
/LOAD_SW
47
/OPEN_SW
/UCS0
UCS1
SRDY
/UNIT0 /UNIT1
/SDIN
/PRST
EXTAL
67
XTAL
8
AUD_MUTE
5
15
2
1
4
3
13
1
3
12
2
5
14
15
4
19
9
OUT IN
+3.3V REG.
IC102
RESET
IC101
CLOCK OSC
IC310
X301
33.8688MHz
SYS BUS
DSP
SERVO
IC201
TP
C34M
FWRST
DA0-DA15
RAM
IC203
RAM
IC302
γ
SDR
γ
LRCK
γ
SCLK
γ
CLK_OUT
PCLK_OUT
PDATA
PLRCK
PSCLK
DUBSEL
CLKSEL<0>
CLKSEL<1>
DUBBING
CLKSEL0
CLKSEL1
P_CLK
CLK_IN
AUD_MUTE
RESET_B
AD_DATA
P_LRCK
P_DATA
MDA_DATA
MDA_LRCK
MDA_CLK
AD_LRCK
P_CLK
AD_CLK
DATA SELECT
IC304
CDR DATA
RXP
SDOUT
OLRCK
OSCLK
OMCK
SDIN
ILRCK
ISCLK
TXP
SDA/CDOUT
AD0/CS
AD1/CDIN
SCL/CCLK
I NT
RST
SRC
IC306
SDAC_MCK
DAC_MCK
OMCK
DATA SELECT
IC307
OPT IN
TXP OUT
MDA_DATA
MDA_LRCK
MDA_CLK
AD_DATA
AD_LRCK
AD_CLK
P_PCMDT
P_LRCK
P_BITCK
SRC_DOUT
SRC_CS
SRC_DIN
SRC_CLK
SRC_INT
SRC_RESET
OPT_SEL
M_PBSEL
S_PBSELT
AS_DUBBING
DUB_SPD0
DUB_SPD1
MCKO
REC_TXD
RW_RXD
REC_CLK
MCLK
SDAC_MCK
MDA_DATA
MDA_LRCK
MDA_CLK
AD_DATA
AD_LRCK
AD_CLK
P_DATA
P_LRCK
P_CLK
OPT_S
M_S
DUBBING
CLKSEL0
CLKSEL1
CDP_33M
DAC_MCLK
SDAC_MCK
CDR_MUTE
AUD.MUTE
IC303
42
RXD
TXD
13
FWMD2
FWEN
S701
(LOADING) TRAY
OPEN
( )
/RST
PN201
D701
OR
X701
20MHz
SYSTEM CONTROL
IC701 (2/2)
RECORD CONTROL
IC301
D+5V
+3.3v
1
CD-R
SECTION
(1/2)
(Page 25)
CDP
SECTION
(Page 27)
AUDIO
SECTION
(Page 28)
2
B
A
CD-R
SECTION
(1/2)
(Page 25)
TEST
CONNECTOR
OUTDATA2 <0>
I
OUTDATA2 <7>
I
I
I
I
I
I
I
I
I
•Signal Path
: CD PLAY
: CD (DIGITAL)
: CD REC