Sony RM-YD024 - FBU Board Schematic Diagram (10 of 18)

KDL-40XBR7
KDL-40XBR7 45
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25
A
—
B
—
C
—
D
—
E
—
F
—
G
—
H
—
I
—
J
—
K
—
L
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M
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N
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O
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P
FBU BOARD SCHEMATIC DIAGRAM (10 OF 18)
SSHSO
FE_VIDEO_MUTE
*RB5301
47
2 1
4 3
6 5
8 7
10
9
12
11
14 13
16 15
*R5300
47
*R5302
68
EPP_DRC_OUT
*R5301
68
*RB5300
68
2 1
4 3
6 5
8 7
10
9
12 11
14 13
16 15
EPP_D3_IN
AD_OUT
22
R5311
22
R5310
R5316
0
14 13 12 11 10 9 8
7123456
TC74VCX74FT(EL)
IC5300
1CLR
1D
1CK
1PR
1Q
1Q
GND 2Q
2Q
2PR
2CK
2D
2CLR
VCC
8765
4321
TC7WZ34FK(TE85R)
IC5301
1A
3Y
2A
GND 2Y
3A
1Y
VCC
BE_3.3V
1005
16V
0.1
C5300
1005
16V
0.1
C5301
CCP1_CK0
CCP2_VS
1/16W
CHIP
5%
47
R5303
CCP1_CK1
CCP1_GAIN_P
47
R5321
47
R5322
47
R5308
COMPANION_OUT
CCP1_HSO
CCP1_VSO
CCP1_CK0
CCP1_CK1
CCP1_GAIN_P
AD4_SEL
AD5_SEL
CCP2_VS
33
R5318
0
R5317
47
R5319
1
2
3
4
5
6
7
8
0uH
L5302
TCON_RDY
1005
25V
0.01
X7R
C5303
PANEL_CTRL2
1
2
3
4
5
6
7
8
0uH
L5305
1005
50V
0.001
X7R
C5302
SET_ON2
BEM_SCL3
1005
16V
0.1
C5304
PANEL_CTRL1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
51P
CN5300
SIL
PANEL_CTRL4
TCON_RDY
PANEL_CTRL3
PANEL_CTRL2
PANEL_CTRL1
FRC_CONT
SET_ON2
PANEL_SEL5
PANEL_CTRL5
VSYNC
SDA3
SCL3
GND
RE[4]P
RE[4]N
RE[3]P
RE[3]N
GND
RECLK+
RECLK-
GND
RE[2]P
RE[2]N
RE[1]P
RE[1]N
RE[0]P
RE[0]N
GND
RO[4]P
RO[4]N
RO[3]P
RO[3]N
GND
ROCLK+
ROCLK-
GND
RO[2]P
RO[2]N
RO[1]P
RO[1]N
RO[0]P
RO[0]N
GND
GND
GND
12V_SW/PANEL_SEL
1
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
0uH
L5303
VS2_IN
1
2
3
4
5
6
7
8
0uH
L5301
1
2
3
4
5
6
7
8
0uH
L5304
LVDS_DLL1.2V
1
2
3
4
5
6
7
8
0uH
L5300
PANEL_CTRL3
CLK0_A
22
*R5325
10k
RB5305
2 1
4 3
6 5
8 7
10k
RB5306
2 1
4 3
6 5
8 7
10
9
12 11
14 13
16 15
10k
RB5307
2 1
4 3
6 5
8 7
10
9
12 11
14 13
16 15
10k
RB5308
2 1
4 3
6 5
8 7
10
9
12 11
14 13
16 15
10k
RB5309
2 1
4 3
6 5
8 7
10
9
12 11
14 13
16 15
10k
RB5310
2 1
4 3
6 5
8 7
10
9
12 11
14 13
16 15
BEM_SDA3
JL5301
*R5304
0
10k
*R5307
PANEL_CTRL5
PANEL_CTRL4
PANEL_SEL5
0
R5341
EMI
FL5300
IC5100
CXD4716BGB
LVDS1_TAM
T4
LVDS1_TAP
T3
LVDS1_TBM
T2
LVDS1_TBP
T1
LVDS1_TCM
R4
LVDS1_TCP
R3
LVDS1_CKM
R2
LVDS1_CKP
R1
LVDS1_TDM
P4
LVDS1_TDP
P3
LVDS1_TEM
P2
LVDS1_TEP
P1
LVDS_DLLVDD
N6
LVDS_DLLVSS
P6
LVDS2_TAM
N4
LVDS2_TAP
N3
LVDS2_TBM
N2
LVDS2_TBP
N1
LVDS2_TCM
M4
LVDS2_TCP
M3
LVDS2_CKM
M2
LVDS2_CKP
M1
LVDS2_TDM
L4
LVDS2_TDP
L3
LVDS2_TEM
L2
LVDS2_TEP
L1
IC5100
CXD4716BGB
VIN1_VS
AN14
VIN1_HS
AM14
VIN1_CK
AP5
VIN1_HSAD
AM13
VIN1_DE
AL14
VIN1_D0
AN13
VIN1_D1
AP13
VIN1_D2
AM12
VIN1_D3
AN12
VIN1_D4
AP12
VIN1_D5
AM11
VIN1_D6
AN11
VIN1_D7
AP11
VIN1_D8
AM10
VIN1_D9
AN10
VIN1_D10
AP10
VIN1_D11
AM9
VIN1_D12
AN9
VIN1_D13
AP9
VIN1_D14
AM8
VIN1_D15
AN8
VIN1_D16
AP8
VIN1_D17
AM7
VIN1_D18
AN7
VIN1_D19
AP7
VIN1_D20
AL13
VIN1_D21
AL12
VIN1_D22
AL11
VIN1_D23
AL10
VIN1_D24
AL9
VIN1_D25
AL8
VIN1_D26
AL7
VIN1_D27
AM6
VIN1_D28
AN6
VIN1_D29
AP6
CCP1_CK
AP14
CCP1_GAIN_P
AN15
CCP1_CLP
AP15
MUTE
AM15
AD4_SEL
AL16
AD5_SEL
AL15
IC5100
CXD4716BGB
VIN3_VS
AM21
VIN3_HS
AN21
VIN3_CK
AP21
VIN3_D0
AM31
VIN3_D1
AN31
VIN3_D2
AP31
VIN3_D3
AL30
VIN3_D4
AM30
VIN3_D5
AN30
VIN3_D6
AP30
VIN3_D7
AL29
VIN3_D8
AM29
VIN3_D9
AN29
VIN3_D10
AP29
VIN3_D11
AL28
VIN3_D12
AM28
VIN3_D13
AN28
VIN3_D14
AP28
VIN3_D15
AL27
VIN3_D16
AM27
VIN3_D17
AN27
VIN3_D18
AP27
VIN3_D19
AL26
VIN3_D20
AM26
VIN3_D21
AN26
VIN3_D22
AP26
VIN3_D23
AL25
VIN3_D24
AM25
VIN3_D25
AN25
VIN3_D26
AP25
VIN3_D27
AL24
VIN3_D28
AM24
VIN3_D29
AN24
VIN3_D30
AP24
VIN3_D31
AL23
VIN3_D32
AM23
VIN3_D33
AN23
VIN3_D34
AP23
VIN3_D35
AL22
VIN3_D36
AM22
VIN3_D37
AN22
VIN3_D38
AP22
VIN3_D39
AL21
CCP2_VS
AM16
CCP2_HS
AN16
CCP2_CK
AP16
CCP2_C0
AL20
CCP2_C1
AM20
CCP2_C2
AN20
CCP2_C3
AP20
CCP2_C4
AL19
CCP2_C5
AM19
CCP2_C6
AN19
CCP2_C7
AP19
CCP2_Y0
AL18
CCP2_Y1
AM18
CCP2_Y2
AN18
CCP2_Y3
AP18
CCP2_Y4
AL17
CCP2_Y5
AM17
CCP2_Y6
AN17
CCP2_Y7
AP17
0
RB5314
0
RB5315
Q32_R[8]
HSO
VSO
DE
Q35_R[11]
Q34_R[10]
Q33_R[9]
Q31_R[7]
Q30_R[6]
Q29_R[5]
Q28_R[4]
Q27_R[3]
Q26_R[2]
Q23_G[11]
Q22_G[10]
Q21_G[9]
Q20_G[8]
Q19_G[7]
Q18_G[6]
Q17_G[5]
Q16_G[4]
Q15_G[3]
Q14_G[2]
Q11_B[11]
Q10_B[10]
Q9_B[9]
Q8_B[8]
Q7_B[7]
Q6_B[6]
Q5_B[5]
Q4_B[4]
Q3_B[3]
Q2_B[2]
EPP_DRC_C2IN0
EPP_DRC_C2IN1
EPP_DRC_C2IN2
EPP_DRC_C2IN3
EPP_DRC_C2IN4
EPP_DRC_C2IN5
EPP_DRC_C2IN6
EPP_DRC_C2IN7
EPP_DRC_C2IN8
EPP_DRC_C2IN9
EPP_DRC_Y2IN7
EPP_DRC_Y2IN6
EPP_DRC_Y2IN4
EPP_DRC_Y2IN3
EPP_DRC_Y2IN2
EPP_DRC_Y2IN0
EPP_DRC_Y2IN1
EPP_DRC_HSIN
ADC_CLAMP
ADC_CLKIN
EPP_DRC_VSIN
EPP_DRC_C1IN0
EPP_DRC_C1IN1
EPP_DRC_C1IN2
EPP_DRC_C1IN3
EPP_DRC_C1IN4
EPP_DRC_C1IN5
EPP_DRC_C1IN6
EPP_DRC_C1IN7
EPP_DRC_C1IN8
EPP_DRC_C1IN9
EPP_DRC_Y1IN0
EPP_DRC_Y1IN1
EPP_DRC_Y1IN2
EPP_DRC_Y1IN3
EPP_DRC_Y1IN4
EPP_DRC_Y1IN5
EPP_DRC_Y1IN6
EPP_DRC_Y1IN7
EPP_DRC_Y1IN8
EPP_DRC_Y1IN9
EPP_DRC_Y2IN7
EPP_DRC_Y2IN6
EPP_DRC_Y2IN5EPP_DRC_Y2IN5
EPP_DRC_Y2IN4
EPP_DRC_Y2IN3
EPP_DRC_Y2IN2
EPP_DRC_Y1IN4
EPP_DRC_Y1IN5
EPP_DRC_Y1IN6
EPP_DRC_Y1IN7
EPP_DRC_Y1IN8
EPP_DRC_Y1IN9
EPP_DRC_Y2IN0
EPP_DRC_Y2IN1
EPP_DRC_C2IN6
EPP_DRC_C2IN7
EPP_DRC_C2IN8
EPP_DRC_C2IN9
EPP_DRC_Y1IN0
EPP_DRC_Y1IN1
EPP_DRC_Y1IN2
EPP_DRC_Y1IN3
EPP_DRC_C1IN8
EPP_DRC_C1IN9
EPP_DRC_C2IN0
EPP_DRC_C2IN1
EPP_DRC_C2IN2
EPP_DRC_C2IN3
EPP_DRC_C2IN4
EPP_DRC_C2IN5
EPP_DRC_C1IN0
EPP_DRC_C1IN1
EPP_DRC_C1IN2
EPP_DRC_C1IN3
EPP_DRC_C1IN4
EPP_DRC_C1IN5
EPP_DRC_C1IN6
EPP_DRC_C1IN7
EPP_DRC_VSIN
EPP_DRC_HSIN
EPP_DRC_Y2IN8
EPP_DRC_Y2IN9
EPP_DRC_Y2IN8
EPP_DRC_Y2IN9
EPP_DRC_CKIN
1M_CLK
1M_HS
1M_VS
1MY0
1MY1
1MY2
1MY3
1MY4
1MY5
1MY6
1MY7
1MC7
1MC6
1MC5
1MC4
1MC3
1MC2
1MC1
1MC0
PORTION2
PORTION4
PORTION6
FBU 10/18
EPP IN/OUT
A-1553-208-B <EZ1> FBU-P10
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