ST STDES-50W2CWBC - Figure 13. STDES-50 W2 CWBC Circuit Schematic (2 of 4)

Figure 13. STDES-50W2CWBC circuit schematic (2 of 4)
Truth Table
IN
Switch S1
L
H
Voltage doubler
Additional NTC
RING_SNS Switch
QF_DRV Switch
C211
50 V X7R
33 0NF
C213
50 V X7R
33 0NF
R219
10 R
1
X1
3
X2
2
COVER2COVER1
4
Y 200
16 M HZ-10 PPM -8P F
R205 NP
C206
35 V
X5R
10 UF
TP 200
R204 10 K
R200 0R 1
C203
X7R
50 V
10 0NF
NTC
R206
47 K
R202
10 K
C212
50 V X7R
33 0NF
R218
3. 3 K 1 %
R201
10 R
R203
15 0 K
R217
47 0 K
D206
SOD5 23
BAT54 KFI LM
R208
10 K
D204
SOD5 23
BAT54 KFI LM
R209 10 K
/I2C
driver
gat e
Boostrap
driver
gate
Boostrap
Main PWM
driver
gate
Boostrap
Analog
Demod
Q- F dri ver
Controller
DCDC
Mai n PWM
PD/QC
Buck
USB
ISns
6
VDD
2
LD O _ 3V3
3
VRE F_A
4
M CU_3V 3
8
M CU_VS S1
60
USB_ DM
59
USB_ DP
11
XTAL_ O UT
10
XTAL_ IN
12
NRST
5
LD O _ 1V8
46
LE D1
47
LE D2
27
VDD _DR
23
SPI_M ISO
24
SPI_M OS I
21
UART _TX
28
HS1_ BT
29
HS1_ G D
30
HS1_ SW
31
LS 1_G D
36
HS2_ BT
35
HS2_ G D
34
HS2_ SW
32
LS 2_G D
41
G ND _DR
9
BUCK _FB
14
BUCK _SW
15
BUCK _BT
16
VIN
22
UART _RX
43
G PIO _ DR1
42
G PIO _ DR0
48
SWDI O
49
SWCL K
25
SPI_NSS
1
IR Q
68
AGND
54
BRG _ VRE F
20
SPI_C LK
19
TE M P SNS
53
BRG _ ISNS _P
52
BRG _ ISNS _M
50
BRG _ VSNS
62
I2 C_S DA
6
STWBC2-HP
3
I2 C_S CL
13
PGND
55
BRG _ IDE M
56
BRG _ FT_ S
57
BRG _ FT_ R
7
M CU_VS S
64
RING _ FT_ S
65
RING _ FT_ R
66
Q F_D RV
69
EPA D
33
DCD C_S NS
17
VIN_ IS NS _P
18
VIN_ IS NS _N
26
VDO UB_ SW
37
HS3_ BT
38
HS3_ G D
39
HS3_ SW
40
LS 3_G D
44
G PIO _ DR2
45
G PIO _ DR3
58
CC1
61
CC2
67
RING _ SNS
51
DCD C_F B
U200
R207
1%
47 K
D205
SOD5 23
BAT54 KFI LM
C200
NP
L2 00
10 uH
D200
RB541 VM -40
D201
VDD _DRVDD _DR
RB541 VM -40
C216
X7R
50 V
10 NF
C221
C0G
50 V
8. 2PF
C222
C0G
50 V
8. 2PF
C227
X7R
50 V
10 NF
C208
C0G
50 V
1NF
C202
X5R
50 V
47 0NF
C215
X7R
25 V
10 0NF
C217
X7R
25 V
10 0NF
C218
X7R
25 V
10 0NF
C223
X7R
25 V
10 0NF
C224
X7R
25 V
10 0NF
C228
C0G
50 V
33 PF
C220 X7R
10 0V
1NF
R220
0 R
NTC
R211
47 K
R210
15 0 K
R213
47 0 K
C225
X7R
50 V
10 NF
1
IN
2
VCC
3
G ND
6
S2
5
D
4
S1
U202
STG 7 19S TR
C226
X7R
25 V
10 0NF
R222
3. 3 K 1 %
R223
1%
47 K
C229
C0G
50 V
33 PF
C230 X7R
10 0V
1NF
D
3
1
G
2
S
Q 202
N-MO S
2N70 02
D
3
1
G
2
S
Q 201
N-MO S
2N70 02
R228
4. 7 K
R227
4. 7 K
C204
16 V
10 UF
X5R
C236
X7R
25 V
10 0NF
C201
X5R
6. 3V
4. 7UF
C234
NP
C235
X5R
6. 3V
4. 7UF
C233
NP
R212 2. 2R
R225 2. 2R
R226 2. 2R
C209
X7R10 0V
5. 6NF
3
D
1
G
S
2
Q 200
N-
M O S
1
IN
2
VCC
3
G ND
6
S2
5
D
4
S1
U201
STG 7 19S TR
C237
X7R
25 V
10 0NF
C231
X7R10 0V
5. 6NF
D
3
1
G
2
S
20 3
BAT54 KFI LM
Q
N-
M O S
D208
BAT54 KFI LM
C214
X7R
50 V
10 NF
C207
X7R
25 V
10 0NF
C238
X7R
6. 3V
1UF
C239
NP
C210
X7R
50 V
10 0NF
4
O UT
5
VCC
3
IN-
1
IN+
2
G ND
U203
LM V321 IL T
R229 10 K R230
0. 1%
33 0 K
C240
COG 50V
1NF
R231
0. 1%
1. 2KR232
0. 1%
9. 1K
C241
X7R
50 V
10 0NF
C242
X7R
50 V
10 0NF
R233
0. 1%
5. 6K
R234
0. 1%
33 0 K
C243
X7R
50 V
10 0NF
J2 01
1
2
3
4
D203
G REE N
D202
RED
D207
R235 10 0 R
R236 10 0 R
D209
G REE N
R237
4. 7 K
VBUC K
3V 3
3V 3
3V 3
VBUC K
VIN
VDC DC
USB_ DP
USB_ DM
SWDI O
SWCL K
UART _TX
UART _RX
SW_HS2
G D_L S2
NRES ET
USB_ CC2
USB_ CC1
G D_HS1
SW_HS1
G D_L S1
G D_HS2
G D_HS3
SW_HS3
G D_L S3
BRIDG E_ISNS_P
RING _ NO DE 1
I2 C_S CL
I2 C_S DA
VIN_ IS NS _N
VIN_ IS NS _P
SW_HS1
FA N
LE D1
LE D2
3V 3
TE M P
TE M P
TA NK 1_S EL
TA NK 2_S EL
TA NK 1_S EL
RING _ SNS
RING _ NO DE 2
RING _ SNS
TA NK 1_S EL
TA NK 2_S EL
Q F_S HO R T
Q F_D RV
VBUC K
BRIDG E_ISNS_N
3V 3 3V 3
I2 C_S CLI 2C _SD A
1V 8
1V 8
RING _ NO DE 1
TA NK 1_S EL
RING _ NO DE 2
Q F_D RV
Q F_S HO R T
VBUC K
VRE FVRE F
VRE F
3V 3 VRE F
BRIDG E_ISNS_P
DCD C_S HO R T
3V 3
I2C_S CL
I2C_S DA
VBUC KVBUC K
LE D1
LE D2
LE D3
3V 3
LE D3
Switch S2
OFF
OFF
ON
ON
/SPI
GPIO
UART
GPIO
TN1399 - Rev 1
page 13/26
TN1399
Schematic diagrams