Debug management
18/29 AN2586 Rev 8
5 Debug management
5.1 Introduction
The Host/Target interface is the hardware equipment that connects the host to the
application board. This interface is made of three components: a hardware debug tool, a
JTAG or SW connector and a cable connecting the host to the debug tool.
Figure 11 shows the connection of the host to the evaluation board (STM3210B-EVAL,
STM3210C-EVAL, STM32100B-EVAL or STM3210E-EVAL).
The Value line evaluation board (STM32100B-EVAL or STM32100E-EVAL) embeds the
debug tools (ST-LINK). Consequently, it can be directly connected to the PC through a USB
cable.
Figure 11. Host-to-board connection
5.2 SWJ debug port (serial wire and JTAG)
The STM32F10xxx core integrates the serial wire/JTAG debug port (SWJ-DP). It is an Arm
®
standard CoreSight™ debug port that combines a JTAG-DP (5-pin) interface and a SW-DP
(2-pin) interface.
• The JTAG debug port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP-
AP port
• The serial wire debug port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG
pins of the JTAG-DP.
5.3 Pinout and debug port pins
The STM32F10xxx MCU is offered in various packages with different numbers of available
pins. As a result, some functionality related to the pin availability may differ from one
package to another.
5.3.1 SWJ debug port pins
Five pins are used as outputs for the SWJ-DP as alternate functions of general-purpose
I/Os (GPIOs). These pins, shown in Table 3, are available on all packages.
Evaluation board
Host PC
Power supply
JTAG/SW connector
Debug tool
ai14866b
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