Direct memory access controller (DMA) RM0440
420/2126 RM0440 Rev 4
12.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx)
Address offset: 0x0C + 0x14 * (x - 1), (x = 1 to 8)
Reset value: 0x0000 0000
12.6.5 DMA channel x peripheral address register (DMA_CPARx)
Address offset: 0x10 + 0x14 * (x - 1), (x = 1 to 8)
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
NDT[15:0]
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Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 NDT[15:0]: number of data to transfer (0 to 2
16
-1)
This field is updated by hardware when the channel is enabled:
– It is decremented after each single DMA ‘read followed by write’ transfer, indicating
the remaining amount of data items to transfer.
– It is kept at zero when the programmed amount of data to transfer is reached, if the
channel is not in circular mode (CIRC = 0 in the DMA_CCRx register).
– It is reloaded automatically by the previously programmed value, when the transfer
is complete, if the channel is in circular mode (CIRC = 1).
If this field is zero, no transfer can be served whatever the channel status (enabled or not).
Note: this field is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA[31:16]
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1514131211109876543210
PA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
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