TM8100/TM8200 Service Manual Description 59
© Tait Electronics Limited November 2007
2.6.2 Frequency Synthesizer
Introduction As shown in Figure 2.16, the frequency synthesizer consists of two main
parts:
■ FCL (frequency control loop)
■ RF PLL, comprising RF PLL device, loop filter, VCO, and VCO output
switch.
Frequency Control
Loop
The FCL consists of the following:
■ TCXO
■ mixer
■ loop filter
■ VCXO
■ frequency control block.
The FCL provides the reference frequency for the RF PLL. The FCL
generates a high-stability reference frequency that can be both modulated
and offset in fine resolution steps.
RF PLL The RF PLL consists of the following:
■ RF PLL device
■ loop filter
■ VCO
■ VCO output switch.
The RF PLL has fast-locking capability but coarse frequency resolution.
This combination of control loops creates improved frequency generation
and acquisition capabilities.
Note that patents are pending for several aspects of the synthesizer design.
Operation of
Control Loop
The RF PLL is a conventional integer-N-type design with frequency
resolution of 25kHz (30kHz for the 66 to 88MHz A4 band). In transmit
mode, the loop locks to the transmit frequency. In receive mode, it locks to
the receive frequency minus the first IF frequency, except for the A4 band,
where it locks to the receive frequency plus the first IF frequency.
In the 762 to 870MHz K5 band, there are two VCOs. In transmit mode,
the loop locks to the transmit frequency. In receive mode, it locks to the
receive frequency plus the first IF frequency when the receiver is operating
in the lower sub-band (762 to 776MHz), and it locks to the receive
frequency minus the first IF frequency when the receiver is operating in the
upper sub-band (850 to 870MHz).
Initially, the VCO generates an unregulated frequency in the required range.
This is fed to the PLL device (ADF4111) and divided down by a
programmed ratio to approximately 25kHz. For the receive VCO in the K5
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