TM8100/TM8200 Service Manual Circuit Descriptions 73
© Tait Electronics Limited November 2007
Frequencies
of IF Stages
The frequency of the first IF stage depends as follows on the frequency band
of the radio:
■ VHF bands: 21.400029MHz
■ UHF and K5 bands: 45.100134MHz.
The above are nominal values; the actual frequency will differ by a small
amount depending on the exact initial frequency of the TCXO.
The frequency of the second IF stage will always be precisely 64.000kHz
once the TCXO calibration has been completed. (The TCXO calibration
does not adjust the TCXO frequency, but instead adjusts the VCXO
frequency, which in turn adjusts the VCO or first LO frequency as well as
the frequency of the first IF stage. The second LO frequency remains fixed.)
The third IF stage is completely within the FPGA and is not accessible.
Demodulation Demodulation takes place within the FPGA. Demodulated audio is passed
to the DSP of the digital board for processing of the receiver audio signal.
Raw demodulated audio can be tapped out from the DSP for use with an
external modem. The modem may be connected to the auxiliary connector
or to the external options connector when an internal options board
is fitted.
Automatic Gain
Control
The receiver has an AGC circuit to enable it to cover a large signal range.
Most of the circuit functions are implemented in the FPGA. The FPGA
passes the AGC signal to the CODEC IC204 for output from pin 14
(
IDACOUT) and then via IC201 as the signal CDC RX AGC to pin 23 of the
quadrature mixer IC400. As the antenna signal increases, the AGC voltage
decreases.
Channel Filtering The channel filtering is split between the first and third IF stages.
The channel filtering circuit in the first IF stage comprises a pair of two-pole
crystal filters. The first filter has a 3dB bandwidth of 12kHz, and the second
a 3dB bandwidth of 15kHz. Most of the channel filtering, however, is
implemented in the FPGA. When the radio is programmed, the different
filters are selected as assigned by the channel programming. The selectable
filters plus the fixed crystal filters result in the following total IF 3dB
bandwidths in Table 3.1:
(The FPGA runs from the
DIG SYS CLK signal, which has a frequency of
12.288MHz.) The receiver requires the TCXO calibration to be completed
to ensure that the channel filtering is centred, thereby minimizing
distortion.
Table 3.1 Total IF 3 dB bandwidths
Channel spacing All bands except K5 K5 band
Wide 12.6kHz 12.00kHz
Medium 12.0kHz 9.0kHz
Narrow 7.8kHz 7.6kHz
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