Specifications
Table 1: A nalog signal acquisition system specifications (cont.)
Characteristic Description
1M 300 V
RMS
at the BNC
Installation Category II
Derate at 20 dB/decade between 4.5 MHz and 45 MHz
Derate 14 dB/decade between 45 MHz and 450 MHz
Above 450 MHz, 5 V
RMS
.
Maximum peak input voltage at the BNC, ±424 V
250 K 75 V
RMS
at the B NC
Installation Category II
Derate at 20 dB/decade between 1.3 MHz and 13 MHz
Derate 10 dB/decade between 13 MHz and 130 MHz
Above 130 MHz, 5 V
RMS
.
Maximum peak input voltage at the BNC, ±106 V
Maximum input
voltage
50 5V
RMS
with peaks ±20 V (Duty Factor 6.25%)
Overvoltage trip is intended to protect against overloads that might damage
termination resistors. A sufficiently large impulse might cause damage
regardless of the overvoltage protection circuitry because of the finite time
required to detect and respond.
DC Balance
0.1 div with the i nput DC coupled, set to 50 termination, and input terminated with 50 BNC terminator
0.2 div at 1 mV/div with the input DC coupled, set to 50 termination, and input terminated with 50
BNC terminator
0.2 div with the input DC coupled, set to 1 M termination, and input terminated with 50 BNC terminator
Number of digitized
bits
8bits
Displayed vertically with 25 digitization levels (DL) per division, 10.24 divisions dynamic range.
"DL" is the abbreviation for "digitization level." A DL is the smallest voltage level change that can be
resolved by an 8-bit A-D Converter. This value is also known as the least significant bit (LSB).
1MΩ 1 m V/div to 10 V/div in a 1-2-5 sequenceSensitivity range
(coarse)
50 Ω 1 mV/div to 1 V/div in a 1-2-5 sequence
1 m V/div to 5 V/div < –50% to > + 50% of selected setting
10 V/div < –50% to 0%
1MΩ
Allows continuous adjustment from 1 mV/div to 10 V/div
1 mV/div to 500 mV/div < –50% to > +50% of selected setting
1 V/div < –50% to 0%
Sensitivity range (fine)
50 Ω
Allows continuous adjustment from 1 mV/div to 1 V/div
Sensitivity resolution
(fine), typical
1% of current setting
2 MDO4000 Series Specifications and Performance Verification