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Product Architecture for Management of Random Faults
4.3.3 Type B: C28x CPU + CLA With Control and Analog Subsystem – Piccolo5x Family
Figure 5. C2000 MCU Piccolo F2805x With Safety Features in Software
Piccolo5x: TMS320F2805x MCU is functionally identical to TMS320F2803x except for the PGA, CAN and
LIN modules. It has a dedicated 32-bit C28x main CPU supports fixed point and IQmath capabilities to
accelerate time critical functions, and control algorithms.
The main CPU has a built-in 40-bit CRC checker, the PSA that can be used to do on-the-fly CRC
calculations for any of the program code or memory blocks. This is a differentiating hardware working in
parallel to the main CPU to estimate the CRC on the memory contents and CPU instructions. The
IEC60730 software libraries have functions using the PSA hardware and details of its use conditions.
While most MCUs can calculate CRC in software using CRC algorithms, the PSA hardware is a feature
that prioritizes instruction and memory level integrity checks and enhances the safety coverage for the
CPU and memory regions. In addition, the Piccolo6x architecture is capable of doing advanced CRC and
math accelerations using its VCU unit. This offers a third method to do memory CRC calculations and
algorithms. These features help to comply with the safety requirements easily.
Piccolo5x memory has non-volatile Flash, OTP Flash, read-only memory (BROM) and RAM blocks. PSA-
based CRC or memory-based CRC and March 13 algorithms are made available to check memory
integrity in periodic and power up software routines.
The system integrator is responsible for the functional partition of these processing engines, depending on
the end application, as each application has different safety reactions and recovery times. The IEC60730
libraries enable easy implementation of safety software using the hardware and software functions.
Control Subsystem: Piccolo5x devices have proven control peripherals such as PWMs, ECAP, and
EQEP modules as part of the MCUs control subsystem. These hardware peripherals are instantiated in
multiple instances on the same chip. This enables redundant channel implementation, thus enabling a
higher level of safety in the end equipment. Having redundant channels enables 1oo2 (1 out of 2
architecture) level voting scheme on critical control channels.
17
SPRUHI3A–April 2013–Revised August 2013 Safety Manual for C2000™ MCUs in IEC60730 Safety Applications
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