LMK04821
,
LMK04826
,
LMK04828
www.ti.com
SNAS605AR –MARCH 2013–REVISED DECEMBER 2015
Revision History (continued)
• Added fixed register setting for 0x172 ................................................................................................................................. 68
• Added LMK04821 register setting ....................................................................................................................................... 91
• Added LMK04821 register setting ....................................................................................................................................... 92
• Changed RB_PLL1_LD description ..................................................................................................................................... 92
• Changed RB_PLL2_LD description ..................................................................................................................................... 92
Changes from Revision AP (June 2013) to Revision AQ Page
• Changed data sheet flow and layout to conform with new TI standards. Added, updated, or renamed the following
sections: Device Information Table, Application and Implementation; Power Supply Recommendations; Layout;
Device and Documentation Support; Mechanical, Packaging, and Ordering Information .................................................... 1
• Added values for LMK04821 under "Features" section. ........................................................................................................ 1
• Changed LMK04820 family to LMK0482x family .................................................................................................................. 1
• Added values for LMK04821 in Device Configuration Information......................................................................................... 6
• Added holdover DAC to pin 36 description in Pin Functions ................................................................................................ 8
• Changed Thermal Information header from LMK0482xB to LMK0482x ............................................................................... 9
• Changed CLKinX_BUF_TYPE to CLKinX_TYPE in Electrical Characteristics .................................................................... 10
• Added values for LMK04821 under Internal VCO Specifications in Electrical Characteristics ............................................ 13
• Added values for LMK04821 under Noise Floor in Electrical Characteristics...................................................................... 14
• Added values for LMK04821 under CLKout Closed Loop Phase Noise Specifications a Commercial Quality VCXO
in Electrical Characteristics .................................................................................................................................................. 15
• Added 245.76 MHz as frequency for LMK04826B phase noise data L(f)
CLKout
for VCO0 ................................................... 16
• Added 245.76 MHz as frequency for LMK04826B phase noise data L(f)
CLKout
for VCO1 ................................................... 16
• Added 245.76 MHz as frequency for LMK04828B phase noise data L(f)
CLKout
for VCO0 ................................................... 16
• Added 245.76 MHz as frequency for LMK04828B phase noise data L(f)
CLKout
for VCO1 ................................................... 16
• Added values for LMK04821 under CLKout Closed Loop Jitter Specifications a Commercial Quality VCXO .................... 17
• Added SDCLKoutY_HS = 0 for ts
JESD204B
in Electrical Characteristics ................................................................................ 19
• Added Propagation Delay from CLKin0 to SDCLKoutY in Electrical Characteristics........................................................... 19
• Added footnote that LMK04821 has no DCLKoutX or SDCLKoutY outputs on at power up, only OSCout. ...................... 19
• Changed V
OH
TEST CONDITIONS to = 3 or 4 and V
OL
TEST CONDITIONS to 3, 4, or 6 under DIGITAL OUTPUTS
(CLKin_SELX, Status_LDX, and RESET/GPO) subheading in Electrical Characteristics................................................... 21
• Changed Digital Inputs (SCK, SDIO, CS*) I
IH
V
IH
= VCC min line from 5 µA to –5 µA........................................................ 22
• Added 4 wire mode read back has same timing as SDIO pin, R/W bit = 0 is for SPI write, R/W bit = 1 is for SPI
read, W1 and W0 shall be written as 0. ............................................................................................................................... 23
• Added LMK04821 phase noise graphs under Clock Output AC Characteristics ................................................................. 24
• Added link to AN-912 Application Report............................................................................................................................. 27
• Changed from Glitchless Half Shift to Glitchless Half Step.................................................................................................. 30
• Added LMK04821 detailed block diagram............................................................................................................................ 32
• Changed block from SDCLKoutY_POL to DCLKoutX_POL in Figure 12 ............................................................................ 34
• Added SYSREF_CLKin0_MUX block to Figure 13 image. .................................................................................................. 35
• Changed Figure 13 to show that FB_MUX SYSREF input comes from SYSREF Divider, not SYSREF_MUX.................. 35
• Changed term pulsor to pulser throughout .......................................................................................................................... 36
• Changed DCLKout0_1_DIV to DCLKout0_DIV; DCLKout2_3_DIV to DCLKout2_DIV; DCLKout4_5_DIV to
DCLKout4_DIV .................................................................................................................................................................... 37
• Added DCLKout4_DIV = 20 ................................................................................................................................................. 37
• Added DCLKout0_DDLY_PD = 0, DCLKout2_DDLY_PD = 0, DCLKout4_DDLY_PD = 0.................................................. 37
• Changed text to read, Set device clock and SYSREF divider digital delays: DCLKout0_DDLY_CNTH,
Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LMK04821 LMK04826 LMK04828
To Next Page
Loading...
Need help?
General
