Figure 9-37. Port Mux Clamp
9.3.4.7 USB2.0 Low-Speed Endpoint
The USB low-speed Endpoint is a USB 2.0 low-speed (1.5 Mbps) interface used to support HID class based
accesses. The TPS65982 supports control of endpoint EP0. This endpoint enumerates to a USB 2.0 bus to
provide USB-Billboard information to a host system as defined in the USB Type-C standard. EP0 is used for
advertising the Billboard Class. When a host is connected to a device that provides Alternate Modes which
cannot be supported by the host, the Billboard class allows a means for the host to report back to the user
without any silent failures.
Figure 9-38 shows the USB Endpoint physical layer. The physical layer consists of the analog transceiver, the
Serial Interface Engine, and the Endpoint FIFOs and supports low speed operation.
Serial
Interface
Engine
Transceiver
LDO_3V3
RPU_EP
EP_TX_DP
1st Stage Mux
USB_RP
1st Stage Mux
USB_RP
C_USB_TP
C_USB_TN
C_USB_BP
C_USB_BN
USB_EP
USB_EP
EP_TX_DN
EP_RX_DP
EP_RX_RCV
EP_RX_DN
2nd Stage
Mux
2nd Stage
Mux
RS_EP
RS_EP
EP0 ( )EP1
TX/RX
FIFO
To Digital
Core
32
RX/TX
Status
Control
Digital Core
Interrupts
and Control
Figure 9-38. USB Endpoint Phy
The transceiver is made up of a fully differential output driver, a differential to single-ended receive buffer and
two single-ended receive buffers on the D+/D– independently. The output driver drives the D+/D– of the selected
output of the Port Multiplexer. The signals pass through the 2
nd
Stage Port Data Multiplexer to the port pins.
When driving, the signal is driven through a source resistance RS_EP. RS_EP is shown as a single resistor in
USB Endpoint Phy but this resistance also includes the resistance of the 2
nd
Stage Port Data Multiplexer defined
www.ti.com
TPS65982
SLVSD02E – MARCH 2015 – REVISED AUGUST 2021
Copyright © 2021 Texas Instruments Incorporated
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