Apalis Carrier Board Design Guide
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Carrier Board Design Guide
This document is a guideline for developing a carrier board that conforms to the specifications
for the Apalis
®
Computer Module
Initial Release: Preliminary Version
Correction in section 4.3
Correction in Figure 23
Correction in Table 10, Table 11, Table 12, and Table 13: signals
USBH_OC# and USBH_EN pin numbers
Correction in Table 16: Description of the pins 282-302
Remove layout guide section (available in a separate document), add
descriptions of low-speed interfaces, minor corrections
Correction of mSATA schematics (Figure 15)
Section 3.5: add information about current consumption budget
Section 2.1.1: update information about preferred interfaces
Section 2.12: add recommendation using MMC1 instead of SD1 as
preferred interface
Section 0: add suitable spacer
Add information about CSI, DSI, and recovery mode
Section 2.5.2.1: Add information about incompatible USB 3.0 OTG
cables
Add missing WAKE1_MICO# pull up resistors in examples
Section 2.4: Add recommendation for TVS diodes in PoE designs
Section 2.4.2: Update recommendation for center tap voltage
Section 2.8.2.2: Correct locations of pull resistors in description
Section 2.13: Clarify 1.8V bus voltage of SD cards
Section 2.13: Add recommendation for SD card power switching
Section 2.19: Clarify and correct Audio AGND recommendations
Section 2.23.2: Update recommendation for unused touch signals
Section 3.2: Correct of POWER_ENABLE_MOCI pull down resistor
Section 3.5: Clarify POWER_ENABLE_MOCI pull down resistor
Section 4.1: Add information regarding alternate module connectors
Section 4.3: Clarify operating temperature range
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