Toradex Apalis Series - Page 4

Apalis Carrier Board Design Guide
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l info@toradex.com
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2.13.2 Reference Schematics ......................................................................................... 48
2.13.3 Unused SD/MMC/SDIO Interface Signal Termination ............................................. 49
2.14 I
2
C .................................................................................................................................... 49
2.14.1 I
2
C Signals .......................................................................................................... 49
2.14.2 Real-Team Clock (RTC) recommendation ............................................................. 49
2.14.3 Unused I
2
C Signal Termination ............................................................................. 50
2.15 UART ................................................................................................................................ 50
2.15.1 UART Signals ...................................................................................................... 50
2.15.2 Reference Schematics ......................................................................................... 51
2.15.3 Unused UART Signal Termination ......................................................................... 53
2.16 SPI ................................................................................................................................... 53
2.16.1 SPI Signals .......................................................................................................... 54
2.16.2 Unused SPI Signal Termination ............................................................................ 54
2.17 CAN .................................................................................................................................. 54
2.17.1 CAN Signals ........................................................................................................ 54
2.17.2 Reference Schematics ......................................................................................... 54
2.17.3 Unused CAN Interface Signal Termination ............................................................. 55
2.18 PWM ................................................................................................................................. 55
2.18.1 PWM Signals ....................................................................................................... 55
2.18.2 Reference Schematics ......................................................................................... 55
2.18.3 Unused PWM Signal Termination .......................................................................... 56
2.19 Analogue Audio ................................................................................................................. 56
2.19.1 Analogue Audio Signals ....................................................................................... 56
2.19.2 Reference Schematics ......................................................................................... 56
2.19.3 Unused Analogue Audio Signal Termination .......................................................... 57
2.20 Digital Audio ...................................................................................................................... 57
2.20.1 Digital Audio Signals ............................................................................................ 57
2.20.2 Reference Schematics ......................................................................................... 57
2.20.3 Unused Digital Audio Interface Signal Termination ................................................. 58
2.21 S/PDIF (Sony-Philips Digital Interface I/O) ........................................................................... 58
2.21.1 S/PDIF Signals .................................................................................................... 58
2.21.2 Reference Schematics ......................................................................................... 58
2.21.3 Unused S/PDIF Interface Signal Termination ......................................................... 59
2.22 Touch Panel Interface ........................................................................................................ 59
2.22.1 Resistive Touch Signals ....................................................................................... 59
2.22.2 Reference Schematics ......................................................................................... 59
2.22.3 Unused Touch Panel Interface Signal Termination ................................................. 60
2.23 Analogue Inputs ................................................................................................................. 60
2.23.1 Analogue Input Signals ......................................................................................... 60
2.23.2 Unused Analogue Inputs Signal Termination .......................................................... 60
2.24 Clock Output ..................................................................................................................... 60
2.24.1 Clock Output Signals ............................................................................................ 60
2.24.2 Schematic and Layout Considerations ................................................................... 60
2.24.3 Unused Clock Output Signal Termination .............................................................. 61
2.25 GPIO ................................................................................................................................ 61
2.25.1 GPIO Signals ....................................................................................................... 61
2.25.2 Unused GPIO Termination .................................................................................... 61
2.26 Module Recovery ............................................................................................................... 62
3 Power Management ........................................................................................................... 63
3.1 Power Signals ................................................................................................................... 63
3.1.1 Digital Supply Signals .............................................................................................. 63
3.1.2 Analogue Supply Signals ......................................................................................... 63
3.1.3 Power Management Signals .................................................................................... 63
3.2 Power Block Diagram ......................................................................................................... 64
3.3 Power States ..................................................................................................................... 64
3.4 Power Sequences .............................................................................................................. 66