Wang 5536 - Page 23

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2.3.1.9 Parity Generation and Check
Memory Parity logic is one of two parity generation/detection circuits.
The other circuit is integral to the Data Link. Memory Parity logic
generates and then tests for even parity on all data transfers leaving or
entering the CPU through the data bus.
During a CPU write,
Memory, CRT Character
memory is enabled.
each parity bit is calculated
Memory, or CRT Control Memory,
and stored in Main
depending upon which
The parity 1 ine is checked on each CPU read. If a Memory Parity Error is
detected the error is noted in the the CPU status register. Such an error
is also indicated in th is register during a CRT control memory write. The
Data Link also tests memory parity before generating its own line parity
during a Master Read command.
A detected memory parity error inunediately freezes the CRT display and
generates all zeroes on the data bus. This is done by disabling the CRT
memory receivers and clearing the character-output buffers. An al 1-zero
data bus is interpreted by the CPU as a string of continuous NOP
instructions. The NOPs disable the CPU while maintaining the necessary
Memory Refresh cycles.
The CPU can es cape from the dis ab 1 ing NOPs only through a Z80A RESET.
Reset can be accomplished by:
o Executing Data ~ink RESTART command
o Accessing Diagnostic PROM
o Cycling AC power.
Following CPU restart, system software attempts to locate the error and to
determine if processor operation should continue despite the error. The
processor may override parity protection. In this mode, parity errors are
indicated on the display by forcing the unuerlining of all CRT characters.
Parity detection circuitry is tested by forcing bad parity to be written
and then reading back the same data location.
2.3.1.10 Z-80A CPU (Figure 2-6)
The Z80A CPU controls workstation logic. CPU signals are sequenced
according to both its internal instruction set and instructions received
from main memory over the data bus. The CPU requires a single +SV DC
supply, and employs a 4 MHz clock as its time base.
Bi-directional data flow is accomplished by an eight-bit, tri-state data
bus. The CPU transmits address information through a sixteen-bit, tri-state
address bus. A reset line initializes the CPU and the six control-output
lines. The six control-output lines are:
o Ml -- CPU Fetch Cycle. This line is active during the first cycle
(fetch cycle) of each instruction-request cycle, and during the special
interrupt cycles.
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