KCU105 Board User Guide www.xilinx.com 94
UG917 (v1.4) September 25, 2015
Appendix C: System Controller
Access the system controller menu as follows:
1. Install the Silicon Labs CP2105GM dual USB-to-UART bridge driver by following the
instructions in the Silicon Labs CP210x USB-to-UART Installation Guide (UG1033)
[Ref 18].
2. The Tera Term terminal application installation is referenced in the driver installation
instructions in step 1, which point to the Tera Term Terminal Emulator Installation Guide
(UG1036) [Ref 19].
3. With the KCU105 evaluation board power turned off, install the USB cable supplied in
the KCU105 evaluation board kit (standard type-A end to host computer, type Micro-B
end to KCU105 evaluation board connector J4).
4. Turn on the KCU105 evaluation board. The PC recognizes that new hardware is
connected, and runs the driver installation wizard to complete the installation of the
CP2015GM bridge chip drivers. The system controller UART appears in the PC device
manager ports (COM &LPT) list as the Silicon Labs Dual CP210x Enhanced COM Port
(COMnn).
5. Open a Tera Term terminal window on the PC desktop. In the New connection dialog
box, click the serial radio button, and then click the drop-down arrow to open the list of
ports. Select the COM port with the Enhanced description. Click OK.
6. At the top of the Tera Term VT window, select Setup > Serial port. In the dialog box that
appears, set baud rate to 115200, data to 8 bit, parity to none, stop to 1 bit, and flow
control to none. Click OK.
7. Power cycle the KCU105 evaluation board. The Tera Term window displays the KCU105
evaluation board system controller main menu.
The main menu lists seven sub-menus that carry out selected actions.
KCU105 System Controller
- Main Menu-
1. Set Programmable Clocks (see Clock Menu)
2. Get Power System (PMBus) Voltages (see PMBus Menu)
3. Get UltraScale FPGA System Monitor (SYSMON) Data (see SYSMON Menu)
4. Adjust FPGA Mezzanine Card (FMC) Settings (see FMC Menu)
5. Get GPIO Data (see GPIO Menu)
6. Get EEPROM Data (see EEPROM Menu)
7. Configure UltraScale FPGA (see CONFIG Menu)
Select an option
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