Xilinx KCU105 User Manual

KCU105 Board User Guide www.xilinx.com 55
UG917 (v1.4) September 25, 2015
Chapter 1: KCU105 Evaluation Board Features
I2C Bus, Topology, and Switches
[Figure 1-2, callouts 21, 22]
The KCU105 evaluation board implements a 2-to-1 I2C bus arrangement. A single I2C bus
from the FPGA U1 XCKU040 (IIC_MAIN_SCL/SDA_LS) and system controller Zynq-7000 AP
SoC U111 (SYSCTLR_I2C_SCL/SDA) is wired to the main I2C bus via level-shifters. FPGA U1 is
wired through level-shifter U77 and system controller U111 is wired through level-shifter
U108. The output sides of U77 and U108 are wired in parallel to the main I2C bus (IIC_SDA
and _SCL_MAIN). This common main I2C bus is then routed to a pair of bus switches, a TI
TCA9548 1-to-8 channel I2C bus switch (U28) and a TI PCA9544 1-to-4 channel I2C bus
switch (U80). The bus switches can operate at speeds up to 400 kHz.
The KCU105 evaluation board I2C bus topology overview is shown in Figure 1-23 and
Tab le 1- 19 lists the address for each device on the I2C bus.
Note:
See Table 1-19 for device I2C address assignments.
X-Ref Target - Figure 1-23
Figure 1-23: I2C Bus Topology Overview
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Xilinx KCU105 Specifications

General

Brand	Xilinx
Model	KCU105
Category	Motherboard
Language	English