Xilinx Kria K26 SOM - Page 16

Table 4: SOM240_1 Signal Pins (cont'd)
Pin Number Signal Name Signal Description
D18 HDA02 HDIO on bank 45
D19 GND Ground
D20 HDA12 HDIO on bank 45
D21 HDA13 HDIO on bank 45
D22 HDA14 HDIO on bank 45
D23 GND Ground
D24 PWRGD_FPD_M2C Power good indication for PS FPD power rails
D25 PWRGD_LPD_M2C Power good indication for PS LPD power rails
D26 PWRGD_PL_M2C Power good indication for all PL power rails
D27 GND Ground
D28 MIO26 PS MIO signal on bank 501. Optional use as PMU input.
D29 MIO27 PS MIO signal on bank 501. Optional use as PMU input.
D30 MIO28 PS MIO signal on bank 501. Optional use as PMU input.
D31 GND Ground
D32 MIO44 PS MIO signal on bank 501
D33 MIO45 PS MIO signal on bank 501
D34 MIO46 PS MIO signal on bank 501
D35 GND Ground
D36 MIO52 PS MIO signal on bank 502
D37 MIO53 PS MIO signal on bank 502
D38 MIO54 PS MIO signal on bank 502
D39 GND Ground
D40 MIO64 PS MIO signal on bank 502
D41 MIO65 PS MIO signal on bank 502
D42 MIO66 PS MIO signal on bank 502
D43 GND Ground
D44 MIO76 PS MIO signal on bank 502
D45 MIO77 PS MIO signal on bank 502
D46 Reserved No connect on the SOM
D47 GND Ground
D48 GND Ground
D49 GTR_DP3_C2M_P PS-GTR lane 3 RX
D50 GTR_DP3_C2M_N PS-GTR lane 3 RX
D51 GND Ground
D52 GND Ground
D53 GTR_REFCLK2_C2M_P PS-GTR REFCLK2 input
D54 GTR_REFCLK2_C2M_N PS-GTR REFCLK2 input
D55 GND Ground
D56 GND Ground
Chapter 2: Electrical Design Considerations
UG1091 (v1.0) April 20, 2021 www.xilinx.com
Carrier Card Design for Kria SOM 16
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