Table 4: SOM240_1 Signal Pins (cont'd)
Pin Number Signal Name Signal Description
C40 MIO57 PS MIO signal on bank 502
C41 GND Ground
C42 MIO67 PS MIO signal on bank 502
C43 MIO68 PS MIO signal on bank 502
C44 MIO69 PS MIO signal on bank 502
C45 Reserved NC on the SOM
C46 GND Ground
C47 GTR_REFCLK0_C2M_P PS-GTR REFCLK0 input
C48 GTR_REFCLK0_C2M_N PS-GTR REFCLK0 input
C49 GND Ground
C50 GND Ground
C51 GTR_DP3_M2C_P PS-GTR lane 3 TX
C52 GTR_DP3_M2C_N PS-GTR lane 3 TX
C53 GND Ground
C54 GND Ground
C55 GTR_DP1_C2M_P PS-GTR lane 1 RX
C56 GTR_DP1_C2M_N PS-GTR lane 1 RX
C57 GND Ground
C58 GND Ground
C59 VCC_SOM SOM main supply voltage, +5V
C60 VCC_SOM SOM main supply voltage, +5V
Connector Row D
D1 VCCO_HPA HPA I/O voltage rail, 1.0V to 1.8V
D2 VCCO_HPA HPA I/O voltage rail, 1.0V to 1.8V
D3 GND Ground
D4 HPA02_P HPIO on bank 66
D5 HPA02_N HPIO on bank 66
D6 GND Ground
D7 HPA01_P HPIO on bank 66
D8 HPA01_N HPIO on bank 66
D9 GND Ground
D10 HPA09_P HPIO on bank 66
D11 HPA09_N HPIO on bank 66
D12 GND Ground
D13 HPA14_P HPIO on bank 66
D14 HPA14_N HPIO on bank 66
D15 GND Ground
D16 HDA00_CC HDIO clock-capable pin on bank 45
D17 HDA01 HDIO on bank 45
Chapter 2: Electrical Design Considerations
UG1091 (v1.0) April 20, 2021 www.xilinx.com
Carrier Card Design for Kria SOM 15
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