EasyManua.ls Logo

Xilinx Kria K26 SOM - Page 19

Xilinx Kria K26 SOM
59 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
SOM240_2 Signal Names and Descriptions
Table 6: SOM240_2 Signal Pins
Pin Number Signal Name Signal Description
Connector Row A
A1 GND Ground
A2 GND Ground
A3 GTH_DP3_C2M_P GTH Lane 3 RX
A4 GTH_DP3_C2M_N GTH Lane 3 RX
A5 GND Ground
A6 GND Ground
A7 GTH_REFCLK1_C2M_P GTH REFCLK1 input
A8 GTH_REFCLK1_C2M_N GTH REFCLK1 input
A9 GND Ground
A10 GND Ground
A11 HPB15_CC_P HPIO clock-capable pin on bank 65
A12 HPB15_CC_N HPIO clock-capable pin on bank 65
A13 GND Ground
A14 HPB08_P HPIO on bank 65
A15 HPB08_N HPIO on bank 65
A16 GND Ground
A17 HPB12_P HPIO on bank 65
A18 HPB12_N HPIO on bank 65
A19 GND Ground
A20 HPB06_P HPIO on bank 65
A21 HPB06_N HPIO on bank 65
A22 GND Ground
A23 HPB16_P HPIO on bank 65
A24 HPB16_N HPIO on bank 65
A25 GND Ground
A26 HPB_19_P HPIO on bank 65
A27 HPB_19_N HPIO on bank 65
A28 GND Ground
A29 HPC08_P HPIO on bank 64
A30 HPC08_N HPIO on bank 64
A31 GND Ground
A32 HPC19_P HPIO on bank 64
A33 HPC19_N HPIO on bank 64
A34 GND Ground
A35 HPC14_P HPIO on bank 64
A36 HPC14_N HPIO on bank 64
Chapter 2: Electrical Design Considerations
UG1091 (v1.0) April 20, 2021 www.xilinx.com
Carrier Card Design for Kria SOM 19
Send Feedback