Xilinx LogiCORE IP Spartan-6 User Manual

Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com 15
UG546 (v1.8) December 14, 2010
Chapter 3
Running the Wizard
Overview
This section provides a step-by-step procedure for generating a Spartan
®
-6 FPGA GTP
transceiver wrapper, implementing the core in hardware using the accompanying example
design, and simulating the core with the provided example test bench.
The example design covered in this section is a wrapper that configures a group of GTP
transceivers for use in a PCI EXPRESS
®
application. Guidelines are also given for
incorporating the wrapper in a design and for the expected behavior in operation.
The PCI EXPRESS example consists of the following components:
• A single GTP transceiver wrapper implementing a four-lane PCI EXPRESS interface
using four GTP transceivers
• A demonstration test bench to drive the example design in simulation
• An example design providing clock signals and connecting an instance of the PCI
EXPRESS wrapper with modules to drive and monitor the wrapper in hardware,
including optional ChipScope™ Pro software support
• Scripts to synthesize and simulate the example design
The Spartan-6 FPGA GTP Transceiver Wizard example design has been tested with XST
12.4 for synthesis and ModelSim 6.5c for simulation.
Figure 3-1 shows a block diagram of the default PCI EXPRESS example design.
X-Ref Target - Figure 3-1
Figure 3-1: Example Design
PCIE Config
Parameters
GTP
Transceiver
Ports
Example Design
GTPA1_DUAL
Tile(s)
GSG546_03_01_021509
PCIE Wrapper
Te st Bench

Xilinx LogiCORE IP Spartan-6 Specifications

General

Device Family	Spartan-6
Maximum Data Rate	3.2 Gbps
Number of Transceivers	Up to 8
Supported Protocols	Gigabit Ethernet
Power Supply	1.0V, 1.2V, 2.5V, 3.3V
Operating Temperature	Commercial, Industrial
Product Name	LogiCORE IP Spartan-6 FPGA Integrated Serial Transceivers