Xilinx LogiCORE IP Spartan-6 - Chapter 5: Detailed Example Design; Directory and File Structure

Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com 45
UG546 (v1.8) December 14, 2010
Chapter 5
Detailed Example Design
This chapter provides detailed information about the example design, including a
description of files and the directory structure generated by the Xilinx
®
CORE Generator™
tool, the purpose and contents of the provided scripts, the contents of the example HDL
wrappers, and the operation of the demonstration test bench.
Directory and File Structure
<project directory>topdirectory
Top-level project directory; name is user-defined
<project directory>/<component name>opdirectory
Core release notes file.
<component name>/doc
Product documentation
<component name>/example design
Verilog and VHDL design files
<component name>/implement
Implementation script files
/implement/results
Results directory, created after implementation scripts are run, and
contains implement script results
<component name>/simulation
Simulation scripts
/simulation/functional
Functional simulation files