Xilinx LogiCORE IP Spartan-6 User Manual

Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com 47
UG546 (v1.8) December 14, 2010
Directory and File Contents
<component name>/doc
The doc directory contains the PDF documentation provided with the core.
<component name>/example design
The example design directory contains the example design files provided with the core.
Table 5-3: Doc Directory
Name Description
<project_dir>/<component_name>/doc
s6_gtpwizard_ds713.pdf
Spartan-6 FPGA GTP Transceiver Wizard v1.8 Data Sheet
s6_gtpwizard_gsg546.pdf
LogiCORE IP Spartan-6 FPGA GTP Transceiver Wizard
v1.8 Getting Started Guide
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Table 5-4: Example Design Directory
Name Description
<project_dir>/<component_name>/example_design
frame_check.v[hd]
Frame-check logic to be instantiated in the
example design.
frame_gen.v[hd]
Frame-generator logic to be instantiated in the
example design.
gtp_attributes.ucf
Constraints file containing the GTP attributes
generated by the GTP Wizard GUI settings.
<component_name>_top.ucf
Constraint file for mapping the GTP wrapper
example design onto a Spartan-6 device.
<component_name>_top.v[hd]
Top-level example design. Contains GTP
transceiver wrapper, reset logic, and
instantiations for frame generator, frame-checker,
and TX sync logic. Also contains definitions for
test frame data and ChipScope™ Pro module
instantiation. See
Figure 3-1, page 15.
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Xilinx LogiCORE IP Spartan-6 Specifications

General

Device Family	Spartan-6
Maximum Data Rate	3.2 Gbps
Number of Transceivers	Up to 8
Supported Protocols	Gigabit Ethernet
Power Supply	1.0V, 1.2V, 2.5V, 3.3V
Operating Temperature	Commercial, Industrial
Product Name	LogiCORE IP Spartan-6 FPGA Integrated Serial Transceivers