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Xilinx LogiCORE IP Spartan-6 User Manual

Xilinx LogiCORE IP Spartan-6
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Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com 21
UG546 (v1.8) December 14, 2010
Generating the Core
Line Rate and Protocol Template
The Line Rate and Protocol Template screen (page 2) of the Wizard (Figure 3-6) allows you
to select the line rate, reference clock frequency, encoding/decoding method, and data
width. In addition, this page specifies protocol templates.
1. Place a check next to the Use Dynamic Reconfiguration Port option if you wish to
bring this signal out for use by the application.
Note: In all of the following tables, options not used by the PCI EXPRESS example are shaded.
The remaining options are divided into GTP0 and GTP1 groups with identical parameters.
These apply to the two GTP transceivers present in each GTPA1_DUAL primitive. The
remaining discussion in this chapter describes only the GTP0 portion.
2. From the Protocol Template list, select Start from scratch if you wish to manually set
all parameters.
Select one of the available protocols from the list to begin your design with a pre-
defined protocol template. For GTP1 only, select Use GTP0 settings to automatically
copy the settings from GTP1. The PCI EXPRESS example uses the pcie protocol
template. Because both transceivers are configured identically, the protocol template
option for GTP1 is set to Use GTP0 settings.
X-Ref Target - Figure 3-6
Figure 3-6: Line Rates and Protocol Template - Page 2

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Xilinx LogiCORE IP Spartan-6 Specifications

General IconGeneral
Device FamilySpartan-6
Maximum Data Rate3.2 Gbps
Number of TransceiversUp to 8
Supported ProtocolsGigabit Ethernet
Power Supply1.0V, 1.2V, 2.5V, 3.3V
Operating TemperatureCommercial, Industrial
Product NameLogiCORE IP Spartan-6 FPGA Integrated Serial Transceivers

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