Xilinx LogiCORE IP Spartan-6 User Manual

Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com 43
UG546 (v1.8) December 14, 2010
Using ChipScope Pro Cores with the Spartan-6 FPGA GTP Transceiver Wizard Core
Using the ISE Simulator
When using the ISE Simulator (ISim), the required Xilinx simulation device libraries are
precompiled, and are updated automatically when service packs and IP updates are
installed. There is no need to run CompXlib to compile libraries, or to manually download
updated libraries.
The wizard also generates a perl script for use with ISim. To run a VHDL or Verilog
simulation of the wrapper, use the following instructions:
1. Set the current directory to
<project_directory>/<component_name>/simulation/functional
2. Launch the simulation script:
• For Windows
- simulate_isim.bat
•For Linux
- % simulate_isim.sh
The ISim script compiles the example design and test bench, and adds the relevant signals
to the wave window.
Using ChipScope Pro Cores with the Spartan-6 FPGA GTP
Transceiver Wizard Core
The ChipScope™ Pro ICON and VIO cores aid in debugging and validating the design in
board. To assist with debugging, these cores are provided with the Spartan-6 FPGA GTP
Transceiver Wizard core, which is enabled by setting USE_CHIPSCOPE as 1 in the
<component_name>_top_example_design file.
Table 4-2: Required ISim Simulation Libraries
HDL Library Source Directories
Verilog UNISIMS_VER < Xilinx dir >/verilog/hdp/<OS>/unisims_ver
VHDL UNISIM < Xilinx dir >/vhdl/hdp/<OS>/unisim
Note: OS refers to the following operating systems: lin, lin64, nt, nt64.

Xilinx LogiCORE IP Spartan-6 Specifications

General

Device Family	Spartan-6
Maximum Data Rate	3.2 Gbps
Number of Transceivers	Up to 8
Supported Protocols	Gigabit Ethernet
Power Supply	1.0V, 1.2V, 2.5V, 3.3V
Operating Temperature	Commercial, Industrial
Product Name	LogiCORE IP Spartan-6 FPGA Integrated Serial Transceivers